| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | fullfp16.s | 93 vcvt.u16.f16 s28, s28, #1
101 @ ARM: vcvt.u16.f16 s28, s28, #1 @ encoding: [0x67,0xe9,0xbf,0xee]
109 @ THUMB: vcvt.u16.f16 s28, s28, #1 @ encoding: [0xbf,0xee,0x67,0xe9]
153 vseleq.f16 s30, s28, s23
154 @ ARM: vseleq.f16 s30, s28, s23 @ encoding: [0x2b,0xf9,0x0e,0xfe]
155 @ THUMB: vseleq.f16 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xf9]
|
| D | fullfp16-neg.s | 71 vcvt.u16.f16 s28, s28, #1
113 vseleq.f16 s30, s28, s23
|
| D | fp-armv8.s | 72 vseleq.f32 s30, s28, s23
73 @ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x2b,0xfa,0x0e,0xfe]
|
| D | thumb-fp-armv8.s | 75 vseleq.f32 s30, s28, s23
76 @ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xfa]
|
| D | simple-fp-encoding.s | 378 vcvt.u16.f32 s28, s28, #1
396 @ CHECK: vcvt.u16.f32 s28, s28, #1 @ encoding: [0x67,0xea,0xbf,0xee]
|
| /external/llvm/test/MC/ARM/ |
| D | fullfp16.s | 93 vcvt.u16.f16 s28, s28, #1
101 @ ARM: vcvt.u16.f16 s28, s28, #1 @ encoding: [0x67,0xe9,0xbf,0xee]
109 @ THUMB: vcvt.u16.f16 s28, s28, #1 @ encoding: [0xbf,0xee,0x67,0xe9]
153 vseleq.f16 s30, s28, s23
154 @ ARM: vseleq.f16 s30, s28, s23 @ encoding: [0x2b,0xf9,0x0e,0xfe]
155 @ THUMB: vseleq.f16 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xf9]
|
| D | fullfp16-neg.s | 71 vcvt.u16.f16 s28, s28, #1
113 vseleq.f16 s30, s28, s23
|
| D | thumb-fp-armv8.s | 75 vseleq.f32 s30, s28, s23
76 @ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xfa]
|
| D | fp-armv8.s | 72 vseleq.f32 s30, s28, s23
73 @ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x2b,0xfa,0x0e,0xfe]
|
| D | simple-fp-encoding.s | 366 vcvt.u16.f32 s28, s28, #1
384 @ CHECK: vcvt.u16.f32 s28, s28, #1 @ encoding: [0x67,0xea,0xbf,0xee]
|
| /external/clang/test/CodeGen/ |
| D | arm-arguments.c | 145 struct s28 { _Complex char f0; }; argument
146 struct s28 f28() {} in f28()
|
| D | arm64-arguments.c | 106 struct s28 { _Complex char f0; }; argument
107 struct s28 f28() {} in f28()
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | fullfp16-arm.txt | 70 # CHECK: vcvt.u16.f16 s28, s28, #1
112 # CHECK: vseleq.f16 s30, s28, s23
|
| D | fullfp16-thumb.txt | 70 # CHECK: vcvt.u16.f16 s28, s28, #1
112 # CHECK: vseleq.f16 s30, s28, s23
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | fullfp16-thumb.txt | 70 # CHECK: vcvt.u16.f16 s28, s28, #1
112 # CHECK: vseleq.f16 s30, s28, s23
|
| D | fullfp16-arm.txt | 70 # CHECK: vcvt.u16.f16 s28, s28, #1
112 # CHECK: vseleq.f16 s30, s28, s23
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceRegistersARM32.def | 65 X(Reg_s28, 28, "s28", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s28, d14, q7)) \
86 X(Reg_d14, 14, "d14", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d14, q7, s28, s29)) \
114 …X(Reg_q7, 7, "q7", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q7, d14, d15, s28, s29, s30…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | spill-fold.ll | 63 …7},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s3…
73 …7},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s3…
|
| D | remat-float0.ll | 15 …7},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s3…
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | remat-float0.ll | 15 …7},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s3…
|
| /external/capstone/suite/MC/ARM/ |
| D | simple-fp-encoding.s.cs | 150 0x67,0xea,0xbf,0xee = vcvt.u16.f32 s28, s28, #1
|
| D | thumb-fp-armv8.s.cs | 30 0x0e,0xfe,0x2b,0xfa = vseleq.f32 s30, s28, s23
|
| D | fp-armv8.s.cs | 30 0x2b,0xfa,0x0e,0xfe = vseleq.f32 s30, s28, s23
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | spill-alloc-sgpr-init-bug.ll | 19 call void asm sideeffect "", "~{s4},~{s8},~{s12},~{s16},~{s20},~{s24},~{s28}" ()
|
| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 224 VIXL_CHECK(AreConsecutive(s26, s27, s28, s29)); in TEST()
252 VIXL_CHECK(!AreConsecutive(s28, s30, NoVReg, NoVReg)); in TEST()
|