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Searched refs:usub8 (Results 1 – 25 of 32) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Darm-cgp-icmps.ll105 ; CHECK-DSP: usub8 r1, r0, r1
143 ; CHECK-DSP-IMM-NEXT: usub8 r0, r0, r1
200 ; CHECK-DSP: usub8 r1, r2, r1
220 ; CHECK-DSP: usub8
257 ; CHECK-DSP: usub8 r1, r0, r1
Dacle-intrinsics.ll156 define i32 @usub8(i32 %a, i32 %b) nounwind {
157 ; CHECK-LABEL: usub8
158 ; CHECK: usub8 r0, r0, r1
159 %tmp = call i32 @llvm.arm.usub8(i32 %a, i32 %b)
443 declare i32 @llvm.arm.usub8(i32, i32) nounwind
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-a32.cc105 M(usub8) \
Dtest-assembler-cond-rd-rn-rm-t32.cc104 M(usub8) \
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs954 0xf5,0x1f,0x58,0xe6 = usub8 r1, r8, r5
Dbasic-thumb2-instructions.s.cs1152 0xc8,0xfa,0x45,0xf1 = usub8 r1, r8, r5
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s2507 usub8 r1, r8, r5
2512 @ CHECK: usub8 r1, r8, r5 @ encoding: [0xf5,0x1f,0x58,0xe6]
Dbasic-thumb2-instructions.s3063 usub8 r1, r8, r5
3069 @ CHECK: usub8 r1, r8, r5 @ encoding: [0xc8,0xfa,0x45,0xf1]
/external/vixl/src/aarch32/
Dassembler-aarch32.h3737 void usub8(Condition cond, Register rd, Register rn, Register rm);
3738 void usub8(Register rd, Register rn, Register rm) { usub8(al, rd, rn, rm); } in usub8() function
Ddisasm-aarch32.h1425 void usub8(Condition cond, Register rd, Register rn, Register rm);
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s3616 usub8 r1, r8, r5
3622 @ CHECK: usub8 r1, r8, r5 @ encoding: [0xc8,0xfa,0x45,0xf1]
Dbasic-arm-instructions.s3427 usub8 r1, r8, r5
3432 @ CHECK: usub8 r1, r8, r5 @ encoding: [0xf5,0x1f,0x58,0xe6]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s3425 usub8 r1, r8, r5
3430 @ CHECK: usub8 r1, r8, r5 @ encoding: [0xf5,0x1f,0x58,0xe6]
Dbasic-thumb2-instructions.s3560 usub8 r1, r8, r5
3566 @ CHECK: usub8 r1, r8, r5 @ encoding: [0xc8,0xfa,0x45,0xf1]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt2245 # CHECK: usub8 r1, r8, r5
Dthumb2.txt2410 # CHECK: usub8 r1, r8, r5
/external/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt2561 # CHECK: usub8 r1, r8, r5
Dbasic-arm-instructions.txt2418 # CHECK: usub8 r1, r8, r5
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt2418 # CHECK: usub8 r1, r8, r5
Dthumb2.txt2561 # CHECK: usub8 r1, r8, r5
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td1966 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
DARMInstrInfo.td3199 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td2239 def t2USUB8 : T2I_pam_intrinsics<0b100, 0b0100, "usub8", int_arm_usub8>;
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td2171 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc7769 "usax\006usub16\005usub8\005uxtab\007uxtab16\005uxtah\004uxtb\006uxtb16\004"
9087 …{ 1706 /* usub8 */, ARM::t2USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|F…
9088 …{ 1706 /* usub8 */, ARM::USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK…

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