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Searched refs:v_cndmask_b32_e64 (Results 1 – 25 of 79) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dudivrem.ll34 ; SI: v_cndmask_b32_e64
38 ; SI: v_cndmask_b32_e64
42 ; SI-DAG: v_cndmask_b32_e64
43 ; SI-DAG: v_cndmask_b32_e64
47 ; SI-DAG: v_cndmask_b32_e64
48 ; SI-DAG: v_cndmask_b32_e64
51 ; SI-DAG: v_cndmask_b32_e64
52 ; SI-DAG: v_cndmask_b32_e64
118 ; SI-DAG: v_cndmask_b32_e64
122 ; SI-DAG: v_cndmask_b32_e64
[all …]
Dsetcc-opt.ll8 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
25 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
42 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
56 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
70 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
84 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
98 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
112 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
155 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
168 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
[all …]
Dffloor.f64.ll18 ; SI: v_cndmask_b32_e64
19 ; SI: v_cndmask_b32_e64
33 ; SI: v_cndmask_b32_e64
34 ; SI: v_cndmask_b32_e64
49 ; SI: v_cndmask_b32_e64
50 ; SI: v_cndmask_b32_e64
Dsetcc.ll101 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
133 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
146 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
160 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
174 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
188 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
339 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
341 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
343 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
360 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
[all …]
Dllvm.amdgcn.class.ll14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
29 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
45 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
61 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
76 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
89 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
104 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
118 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
132 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
150 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
[all …]
Dfract.f64.ll17 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
18 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
44 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
45 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
72 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
73 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
Dsetcc64.ll62 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
83 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
95 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
106 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
117 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
128 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
Dtrunc-cmp-constant.ll8 ; SI: v_cndmask_b32_e64
24 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]
121 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]
136 ; XSI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CMP0]]
160 ; SI-NEXT: v_cndmask_b32_e64
Dsgpr-control-flow.ll68 ; SI: v_cndmask_b32_e64 [[V_CMP:v[0-9]+]], 0, -1, [[CMP_IF]]
73 ; SI: v_cndmask_b32_e64 [[V_CMP]], 0, -1, [[CMP_ELSE]]
76 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP_CMP]]
Dv_cndmask.ll7 ; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}}
27 ; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}}
Dcndmask-no-def-vcc.ll10 ; GCN: v_cndmask_b32_e64 v1, 0, 1, s{{\[[0-9]+:[0-9]+\]}}
37 ; GCN: v_cndmask_b32_e64 v1, 0, 1, s{{\[[0-9]+:[0-9]+\]}}
Duint_to_fp.ll81 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
92 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0
105 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dudivrem.ll35 ; SI: v_cndmask_b32_e64 [[CND1:v[0-9]+]], [[RCP_LO]], [[NEG_RCP_LO]], [[CC1]]
39 ; SI: v_cndmask_b32_e64 [[CND2:v[0-9]+]], [[RCP_S_E]], [[RCP_A_E]], [[CC1]]
44 ; SI-DAG: v_cndmask_b32_e64
47 ; SI-DAG: v_cndmask_b32_e64
48 ; SI-DAG: v_cndmask_b32_e64
50 ; SI-DAG: v_cndmask_b32_e64
51 ; SI-DAG: v_cndmask_b32_e64
118 ; SI-DAG: v_cndmask_b32_e64
122 ; SI-DAG: v_cndmask_b32_e64
126 ; SI-DAG: v_cndmask_b32_e64
[all …]
Ddagcombine-select.ll106 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 9,
127 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, [[F]], -3,
147 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 9,
148 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 6, 5,
149 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 10, 6,
150 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 14, 7,
159 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 5, 0,
168 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 5, 0,
177 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 3, 33,
186 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 3, 33,
[all …]
Dllvm.amdgcn.class.f16.ll10 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
31 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
53 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
75 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
96 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
112 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
129 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, vcc
146 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, vcc
Dsetcc-opt.ll8 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
25 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
42 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
56 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
70 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
84 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
98 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
112 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
159 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
172 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
[all …]
Didiv-licm.ll12 ; GCN-DAG: v_cndmask_b32_e64
16 ; GCN-DAG: v_cndmask_b32_e64
48 ; GCN-DAG: v_cndmask_b32_e64
52 ; GCN-DAG: v_cndmask_b32_e64
84 ; GCN-DAG: v_cndmask_b32_e64
88 ; GCN-DAG: v_cndmask_b32_e64
120 ; GCN-DAG: v_cndmask_b32_e64
124 ; GCN-DAG: v_cndmask_b32_e64
Dllvm.amdgcn.class.ll14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
29 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
45 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
61 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
76 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
89 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
104 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
118 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
132 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
150 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
[all …]
Dsetcc.ll107 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
139 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
152 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
166 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
180 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
194 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
345 ; GCN-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
347 ; GCN-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
349 ; GCN-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
366 ; GCN-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
[all …]
Dfcmp.f16.ll11 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
37 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
62 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
85 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
108 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
131 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
154 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
177 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
200 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
223 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
[all …]
Dsetcc64.ll62 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
83 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
95 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
106 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
117 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
128 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
Dtrunc-cmp-constant.ll10 ; SI: v_cndmask_b32_e64
26 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]
123 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]
138 ; XSI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CMP0]]
163 ; SI-NEXT: v_cndmask_b32_e64
Dllvm.amdgcn.wqm.vote.ll6 ;CHECK: v_cndmask_b32_e64 v0, 0, 1.0, [[WQM]]
37 ;CHECK: v_cndmask_b32_e64 [[KILL:[^,]+]], -1.0, 1.0, [[WQM]]
Dsign_extend.ll5 ; GCN: v_cndmask_b32_e64
27 ; GCN: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc
67 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1
81 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1
93 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dvop-err.s114 v_cndmask_b32_e64 v0, s1, v2, vcc label
117 v_cndmask_b32_e64 v0, flat_scratch_lo, v2, vcc label
120 v_cndmask_b32_e64 v0, flat_scratch_hi, v2, vcc label
123 v_cndmask_b32_e64 v0, s1, v2, flat_scratch label
126 v_cndmask_b32_e64 v0, s0, v2, s[0:1] label
129 v_cndmask_b32_e64 v0, v2, s0, s[0:1] label
132 v_cndmask_b32_e64 v0, s0, s0, s[0:1] label
135 v_cndmask_b32_e64 v0, s1, v2, s[0:1] label
138 v_cndmask_b32_e64 v0, v2, s1, s[0:1] label
141 v_cndmask_b32_e64 v0, s1, s1, s[0:1] label
[all …]

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