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/external/llvm/test/CodeGen/ARM/
Dfp16-promote.ll9 ; CHECK-FP16: vcvtb.f32.f16
10 ; CHECK-FP16: vcvtb.f32.f16
15 ; CHECK-FP16: vcvtb.f16.f32
26 ; CHECK-FP16: vcvtb.f32.f16
27 ; CHECK-FP16: vcvtb.f32.f16
32 ; CHECK-FP16: vcvtb.f16.f32
43 ; CHECK-FP16: vcvtb.f32.f16
44 ; CHECK-FP16: vcvtb.f32.f16
49 ; CHECK-FP16: vcvtb.f16.f32
60 ; CHECK-FP16: vcvtb.f32.f16
[all …]
Dfp16-v3.ll7 ; CHECK-DAG: vcvtb.f32.f16 [[SREG1:s[0-9]+]],
9 ; CHECK-DAG: vcvtb.f16.f32 [[SREG3:s[0-9]+]], [[SREG2]]
10 ; CHECK-DAG: vcvtb.f32.f16 [[SREG4:s[0-9]+]], [[SREG3]]
12 ; CHECK-NEXT: vcvtb.f16.f32 [[SREG6:s[0-9]+]], [[SREG5]]
31 ; CHECK: vcvtb.f16.f32
32 ; CHECK: vcvtb.f16.f32
33 ; CHECK: vcvtb.f16.f32
Dhalf.ll34 ; CHECK-F16: vcvtb.f32.f16
35 ; CHECK-V8: vcvtb.f32.f16
46 ; CHECK-F16: vcvtb.f32.f16
48 ; CHECK-V8: vcvtb.f64.f16
58 ; CHECK-F16: vcvtb.f16.f32
59 ; CHECK-V8: vcvtb.f16.f32
70 ; CHECK-V8: vcvtb.f16.f64
Dfp16-args.ll24 ; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}}
25 ; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}}
27 ; SOFT: vcvtb.f16.f32 {{s[0-9]+}}, {{s[0-9]+}}
32 ; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s1
33 ; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s0
35 ; HARD: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{s[0-9]+}}
Dfp16.ll31 ; CHECK-FP16: vcvtb.f32.f16
32 ; CHECK-ARMv8: vcvtb.f32.f16
38 ; CHECK-FP16: vcvtb.f32.f16
39 ; CHECK-ARMV8: vcvtb.f32.f16
46 ; CHECK-FP16: vcvtb.f16.f32
47 ; CHECK-ARMV8: vcvtb.f16.f32
66 ; CHECK-FP16: vcvtb.f32.f16 [[TMP32:s[0-9]+]], [[TMP16]]
70 ; CHECK-ARMV8: vcvtb.f64.f16 d0, [[TMP]]
90 ; CHECK-FP16-UNSAFE-NEXT: vcvtb.f16.f32 s0, s0
92 ; CHECK-ARMV8: vcvtb.f16.f64 [[TMP:s[0-9]+]], d0
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dfp16-promote.ll9 ; CHECK-FP16: vcvtb.f32.f16
10 ; CHECK-FP16: vcvtb.f32.f16
15 ; CHECK-FP16: vcvtb.f16.f32
26 ; CHECK-FP16: vcvtb.f32.f16
27 ; CHECK-FP16: vcvtb.f32.f16
32 ; CHECK-FP16: vcvtb.f16.f32
43 ; CHECK-FP16: vcvtb.f32.f16
44 ; CHECK-FP16: vcvtb.f32.f16
49 ; CHECK-FP16: vcvtb.f16.f32
60 ; CHECK-FP16: vcvtb.f32.f16
[all …]
Dhalf.ll34 ; CHECK-F16: vcvtb.f32.f16
35 ; CHECK-V8: vcvtb.f32.f16
46 ; CHECK-F16: vcvtb.f32.f16
48 ; CHECK-V8: vcvtb.f64.f16
58 ; CHECK-F16: vcvtb.f16.f32
59 ; CHECK-V8: vcvtb.f16.f32
70 ; CHECK-V8: vcvtb.f16.f64
Dfp16-v3.ll9 ; CHECK-DAG: vcvtb.f16.f32 [[SREG3:s[0-9]+]], [[SREG2]]
10 ; CHECK-DAG: vcvtb.f32.f16 [[SREG4:s[0-9]+]], [[SREG3]]
12 ; CHECK-NEXT: vcvtb.f16.f32 [[SREG6:s[0-9]+]], [[SREG5]]
31 ; CHECK: vcvtb.f16.f32
32 ; CHECK: vcvtb.f16.f32
33 ; CHECK: vcvtb.f16.f32
Dfp16-args.ll24 ; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}}
25 ; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}}
27 ; SOFT: vcvtb.f16.f32 {{s[0-9]+}}, {{s[0-9]+}}
32 ; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s1
33 ; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s0
35 ; HARD: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{s[0-9]+}}
Dfp16.ll31 ; CHECK-FP16: vcvtb.f32.f16
32 ; CHECK-ARMV8: vcvtb.f32.f16
38 ; CHECK-FP16: vcvtb.f32.f16
39 ; CHECK-ARMV8: vcvtb.f32.f16
46 ; CHECK-FP16: vcvtb.f16.f32
47 ; CHECK-ARMV8: vcvtb.f16.f32
66 ; CHECK-FP16: vcvtb.f32.f16 [[TMP32:s[0-9]+]], [[TMP16]]
70 ; CHECK-ARMV8: vcvtb.f64.f16 d0, [[TMP]]
90 ; CHECK-FP16-UNSAFE-NEXT: vcvtb.f16.f32 s0, s0
92 ; CHECK-ARMV8: vcvtb.f16.f64 [[TMP:s[0-9]+]], d0
Dfp16-instructions.ll77 ; CHECK-SOFTFP-FP16: vcvtb.f32.f16 [[S2]], [[S2]]
78 ; CHECK-SOFTFP-FP16: vcvtb.f32.f16 [[S0]], [[S0]]
80 ; CHECK-SOFTFP-FP16: vcvtb.f16.f32 [[S0]], [[S0]]
96 ; CHECK-HARDFP-FP16: vcvtb.f32.f16 [[S2:s[0-9]]], s1
97 ; CHECK-HARDFP-FP16: vcvtb.f32.f16 [[S0:s[0-9]]], s0
99 ; CHECK-HARDFP-FP16: vcvtb.f16.f32 [[S0]], [[S0]]
124 ; CHECK-SOFTFP-FP16: vcvtb.f32.f16 s{{.}}, s{{.}}
125 ; CHECK-SOFTFP-FP16: vcvtb.f32.f16 s{{.}}, s{{.}}
214 ; CHECK-SOFTFP-FP16: vcvtb.f32.f16 [[S2:s[0-9]]], [[S2]]
287 ; CHECK-HARDFP-FULLFP16: vcvtb.f16.f32 s0, s0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-vcvt-fp16.s13 @ CHECK-FP16: vcvtb.f32.f16 s7, s1 @ encoding: [0x60,0x3a,0xf2,0xee]
15 vcvtb.f32.f16 s7, s1
16 @ CHECK-FP16: vcvtb.f16.f32 s1, s7 @ encoding: [0x63,0x0a,0xf3,0xee]
18 vcvtb.f16.f32 s1, s7
Dfp-armv8.s10 vcvtb.f64.f16 d3, s1
11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0x60,0x3b,0xb2,0xee]
12 vcvtb.f16.f64 s4, d1
13 @ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0x41,0x2b,0xb3,0xee]
Dthumb-fp-armv8.s10 vcvtb.f64.f16 d3, s1
11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0x60,0x3b]
12 vcvtb.f16.f64 s4, d1
13 @ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0xb3,0xee,0x41,0x2b]
Ddirective-arch_extension-fp.s48 vcvtb.f64.f16 d0, s0
50 vcvtb.f16.f64 s0, d0
184 vcvtb.f64.f16 d0, s0
186 vcvtb.f16.f64 s0, d0
/external/llvm/test/MC/ARM/
Dneon-vcvt-fp16.s13 @ CHECK-FP16: vcvtb.f32.f16 s7, s1 @ encoding: [0x60,0x3a,0xf2,0xee]
15 vcvtb.f32.f16 s7, s1
16 @ CHECK-FP16: vcvtb.f16.f32 s1, s7 @ encoding: [0x63,0x0a,0xf3,0xee]
18 vcvtb.f16.f32 s1, s7
Dthumb-fp-armv8.s10 vcvtb.f64.f16 d3, s1
11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0x60,0x3b]
12 vcvtb.f16.f64 s4, d1
13 @ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0xb3,0xee,0x41,0x2b]
Dfp-armv8.s10 vcvtb.f64.f16 d3, s1
11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0x60,0x3b,0xb2,0xee]
12 vcvtb.f16.f64 s4, d1
13 @ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0x41,0x2b,0xb3,0xee]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dfp16.ll18 ; CHECK-FP16: vcvtb.f16.f32
21 ; CHECK-FP16: vcvtb.f16.f32
25 ; CHECK-FP16: vcvtb.f32.f16
/external/capstone/suite/MC/ARM/
Dthumb-fp-armv8.s.cs4 0xb2,0xee,0x60,0x3b = vcvtb.f64.f16 d3, s1
5 0xb3,0xee,0x41,0x2b = vcvtb.f16.f64 s4, d1
Dfp-armv8.s.cs4 0x60,0x3b,0xb2,0xee = vcvtb.f64.f16 d3, s1
5 0x41,0x2b,0xb3,0xee = vcvtb.f16.f64 s4, d1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dfp-armv8.txt10 # CHECK: vcvtb.f64.f16 d3, s1
13 # CHECK: vcvtb.f16.f64 s4, d1
Dthumb-fp-armv8.txt10 # CHECK: vcvtb.f64.f16 d3, s1
13 # CHECK: vcvtb.f16.f64 s4, d1
/external/llvm/test/MC/Disassembler/ARM/
Dfp-armv8.txt10 # CHECK: vcvtb.f64.f16 d3, s1
13 # CHECK: vcvtb.f16.f64 s4, d1
Dthumb-fp-armv8.txt10 # CHECK: vcvtb.f64.f16 d3, s1
13 # CHECK: vcvtb.f16.f64 s4, d1

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