Home
last modified time | relevance | path

Searched refs:vrsqrte (Results 1 – 25 of 54) sorted by relevance

123

/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-reciprocal-encoding.s15 @ CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xa0,0x04,0xfb,0xf3]
16 vrsqrte.u32 d16, d16
17 @ CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xe0,0x04,0xfb,0xf3]
18 vrsqrte.u32 q8, q8
19 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3]
20 vrsqrte.f32 d16, d16
21 @ CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xe0,0x05,0xfb,0xf3]
22 vrsqrte.f32 q8, q8
Dneont2-reciprocal-encoding.s17 @ CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x04]
18 vrsqrte.u32 d16, d16
19 @ CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x04]
20 vrsqrte.u32 q8, q8
21 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x05]
22 vrsqrte.f32 d16, d16
23 @ CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x05]
24 vrsqrte.f32 q8, q8
/external/llvm/test/MC/ARM/
Dneon-reciprocal-encoding.s15 @ CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xa0,0x04,0xfb,0xf3]
16 vrsqrte.u32 d16, d16
17 @ CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xe0,0x04,0xfb,0xf3]
18 vrsqrte.u32 q8, q8
19 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3]
20 vrsqrte.f32 d16, d16
21 @ CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xe0,0x05,0xfb,0xf3]
22 vrsqrte.f32 q8, q8
Dneont2-reciprocal-encoding.s17 @ CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x04]
18 vrsqrte.u32 d16, d16
19 @ CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x04]
20 vrsqrte.u32 q8, q8
21 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x05]
22 vrsqrte.f32 d16, d16
23 @ CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x05]
24 vrsqrte.f32 q8, q8
Dfullfp16-neon.s240 vrsqrte.f16 d0, d1
241 vrsqrte.f16 q0, q1
242 @ ARM: vrsqrte.f16 d0, d1 @ encoding: [0x81,0x05,0xb7,0xf3]
243 @ ARM: vrsqrte.f16 q0, q1 @ encoding: [0xc2,0x05,0xb7,0xf3]
244 @ THUMB: vrsqrte.f16 d0, d1 @ encoding: [0xb7,0xff,0x81,0x05]
245 @ THUMB: vrsqrte.f16 q0, q1 @ encoding: [0xb7,0xff,0xc2,0x05]
Dfullfp16-neon-neg.s175 vrsqrte.f16 d0, d1
176 vrsqrte.f16 q0, q1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-reciprocal-encoding.s15 @ CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xa0,0x04,0xfb,0xf3]
16 vrsqrte.u32 d16, d16
17 @ CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xe0,0x04,0xfb,0xf3]
18 vrsqrte.u32 q8, q8
19 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3]
20 vrsqrte.f32 d16, d16
21 @ CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xe0,0x05,0xfb,0xf3]
22 vrsqrte.f32 q8, q8
Dneont2-reciprocal-encoding.s17 @ CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x04]
18 vrsqrte.u32 d16, d16
19 @ CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x04]
20 vrsqrte.u32 q8, q8
21 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x05]
22 vrsqrte.f32 d16, d16
23 @ CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x05]
24 vrsqrte.f32 q8, q8
Dfullfp16-neon.s240 vrsqrte.f16 d0, d1
241 vrsqrte.f16 q0, q1
242 @ ARM: vrsqrte.f16 d0, d1 @ encoding: [0x81,0x05,0xb7,0xf3]
243 @ ARM: vrsqrte.f16 q0, q1 @ encoding: [0xc2,0x05,0xb7,0xf3]
244 @ THUMB: vrsqrte.f16 d0, d1 @ encoding: [0xb7,0xff,0x81,0x05]
245 @ THUMB: vrsqrte.f16 q0, q1 @ encoding: [0xb7,0xff,0xc2,0x05]
/external/llvm/test/CodeGen/ARM/
Dvrec.ll64 ;CHECK: vrsqrte.u32
66 %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
72 ;CHECK: vrsqrte.u32
74 %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
80 ;CHECK: vrsqrte.f32
82 %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
88 ;CHECK: vrsqrte.f32
90 %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
94 declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
95 declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
[all …]
D2009-11-01-NeonMoves.ll23 …%8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses…
38 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvrec.ll64 ;CHECK: vrsqrte.u32
66 %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
72 ;CHECK: vrsqrte.u32
74 %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
80 ;CHECK: vrsqrte.f32
82 %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
88 ;CHECK: vrsqrte.f32
90 %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
94 declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
95 declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
[all …]
D2009-11-01-NeonMoves.ll23 …%8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses…
38 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
Dreg_sequence.ll194 ; CHECK: vrsqrte.f32 q8, q8
206 …%1 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %0) nounwind ; <<4 x float>> [#uses…
348 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvrec.ll64 ;CHECK: vrsqrte.u32
66 %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
72 ;CHECK: vrsqrte.u32
74 %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
80 ;CHECK: vrsqrte.f32
82 %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
88 ;CHECK: vrsqrte.f32
90 %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
94 declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
95 declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
[all …]
D2009-11-01-NeonMoves.ll23 …%8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses…
38 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
/external/capstone/suite/MC/ARM/
Dneont2-reciprocal-encoding.s.cs8 0xfb,0xff,0xa0,0x04 = vrsqrte.u32 d16, d16
9 0xfb,0xff,0xe0,0x04 = vrsqrte.u32 q8, q8
10 0xfb,0xff,0xa0,0x05 = vrsqrte.f32 d16, d16
11 0xfb,0xff,0xe0,0x05 = vrsqrte.f32 q8, q8
Dneon-reciprocal-encoding.s.cs8 0xa0,0x04,0xfb,0xf3 = vrsqrte.u32 d16, d16
9 0xe0,0x04,0xfb,0xf3 = vrsqrte.u32 q8, q8
10 0xa0,0x05,0xfb,0xf3 = vrsqrte.f32 d16, d16
11 0xe0,0x05,0xfb,0xf3 = vrsqrte.f32 q8, q8
/external/arm-neon-tests/
Dref_vrsqrte.c43 vrsqrte##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \ in exec_vrsqrte()
DMakefile.gcc60 vqrshrun_n vstX_lane vtbX vrecpe vrsqrte vcage vcagt vcale \
DMakefile54 vqrshrun_n vstX_lane vtbX vrecpe vrsqrte vcage vcagt vcale \
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-thumb.txt153 # CHECK: vrsqrte.f16 d0, d1
154 # CHECK: vrsqrte.f16 q0, q1
Dfullfp16-neon-arm.txt153 # CHECK: vrsqrte.f16 d0, d1
154 # CHECK: vrsqrte.f16 q0, q1
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-thumb.txt153 # CHECK: vrsqrte.f16 d0, d1
154 # CHECK: vrsqrte.f16 q0, q1
Dfullfp16-neon-arm.txt153 # CHECK: vrsqrte.f16 d0, d1
154 # CHECK: vrsqrte.f16 q0, q1

123