1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "CUnit/Basic.h"
25
26 #include "amdgpu_test.h"
27 #include "amdgpu_drm.h"
28 #include "amdgpu_internal.h"
29
30 static amdgpu_device_handle device_handle;
31 static uint32_t major_version;
32 static uint32_t minor_version;
33
34
35 static void amdgpu_vmid_reserve_test(void);
36
suite_vm_tests_enable(void)37 CU_BOOL suite_vm_tests_enable(void)
38 {
39 CU_BOOL enable = CU_TRUE;
40
41 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
42 &minor_version, &device_handle))
43 return CU_FALSE;
44
45 if (device_handle->info.family_id == AMDGPU_FAMILY_SI) {
46 printf("\n\nCurrently hangs the CP on this ASIC, VM suite disabled\n");
47 enable = CU_FALSE;
48 }
49
50 if (amdgpu_device_deinitialize(device_handle))
51 return CU_FALSE;
52
53 return enable;
54 }
55
suite_vm_tests_init(void)56 int suite_vm_tests_init(void)
57 {
58 int r;
59
60 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
61 &minor_version, &device_handle);
62
63 if (r) {
64 if ((r == -EACCES) && (errno == EACCES))
65 printf("\n\nError:%s. "
66 "Hint:Try to run this test program as root.",
67 strerror(errno));
68 return CUE_SINIT_FAILED;
69 }
70
71 return CUE_SUCCESS;
72 }
73
suite_vm_tests_clean(void)74 int suite_vm_tests_clean(void)
75 {
76 int r = amdgpu_device_deinitialize(device_handle);
77
78 if (r == 0)
79 return CUE_SUCCESS;
80 else
81 return CUE_SCLEAN_FAILED;
82 }
83
84
85 CU_TestInfo vm_tests[] = {
86 { "resere vmid test", amdgpu_vmid_reserve_test },
87 CU_TEST_INFO_NULL,
88 };
89
amdgpu_vmid_reserve_test(void)90 static void amdgpu_vmid_reserve_test(void)
91 {
92 amdgpu_context_handle context_handle;
93 amdgpu_bo_handle ib_result_handle;
94 void *ib_result_cpu;
95 uint64_t ib_result_mc_address;
96 struct amdgpu_cs_request ibs_request;
97 struct amdgpu_cs_ib_info ib_info;
98 struct amdgpu_cs_fence fence_status;
99 uint32_t expired, flags;
100 int i, r;
101 amdgpu_bo_list_handle bo_list;
102 amdgpu_va_handle va_handle;
103 static uint32_t *ptr;
104
105 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
106 CU_ASSERT_EQUAL(r, 0);
107
108 flags = 0;
109 r = amdgpu_vm_reserve_vmid(device_handle, flags);
110 CU_ASSERT_EQUAL(r, 0);
111
112
113 r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
114 AMDGPU_GEM_DOMAIN_GTT, 0,
115 &ib_result_handle, &ib_result_cpu,
116 &ib_result_mc_address, &va_handle);
117 CU_ASSERT_EQUAL(r, 0);
118
119 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
120 &bo_list);
121 CU_ASSERT_EQUAL(r, 0);
122
123 ptr = ib_result_cpu;
124
125 for (i = 0; i < 16; ++i)
126 ptr[i] = 0xffff1000;
127
128 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
129 ib_info.ib_mc_address = ib_result_mc_address;
130 ib_info.size = 16;
131
132 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
133 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
134 ibs_request.ring = 0;
135 ibs_request.number_of_ibs = 1;
136 ibs_request.ibs = &ib_info;
137 ibs_request.resources = bo_list;
138 ibs_request.fence_info.handle = NULL;
139
140 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
141 CU_ASSERT_EQUAL(r, 0);
142
143
144 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
145 fence_status.context = context_handle;
146 fence_status.ip_type = AMDGPU_HW_IP_GFX;
147 fence_status.ip_instance = 0;
148 fence_status.ring = 0;
149 fence_status.fence = ibs_request.seq_no;
150
151 r = amdgpu_cs_query_fence_status(&fence_status,
152 AMDGPU_TIMEOUT_INFINITE,0, &expired);
153 CU_ASSERT_EQUAL(r, 0);
154
155 r = amdgpu_bo_list_destroy(bo_list);
156 CU_ASSERT_EQUAL(r, 0);
157
158 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
159 ib_result_mc_address, 4096);
160 CU_ASSERT_EQUAL(r, 0);
161
162 flags = 0;
163 r = amdgpu_vm_unreserve_vmid(device_handle, flags);
164 CU_ASSERT_EQUAL(r, 0);
165
166
167 r = amdgpu_cs_ctx_free(context_handle);
168 CU_ASSERT_EQUAL(r, 0);
169 }
170