README.altera_spi
1SoCFPGA EPCS/EPCQx1 mini howto:
2- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
3- The controller base address is the "Base" in QSys + 0x400
4- Set MSEL[4:0]=10010 (AS Standard)
5- Load the bitstream into FPGA, enable bridges
6- Only then will the driver work
7
README.dual-flash
1SPI/QSPI Dual flash connection modes:
2=====================================
3
4This describes how SPI/QSPI flash memories are connected to a given
5controller in a single chip select line.
6
7Current spi_flash framework supports, single flash memory connected
8to a given controller with single chip select line, but there are some
9hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
10connected with a single chip select line from a controller.
11
12"dual_flash" from include/spi.h describes these types of connection mode
13
14Possible connections:
15--------------------
16SF_SINGLE_FLASH:
17 - single spi flash memory connected with single chip select line.
18
19 +------------+ CS +---------------+
20 | |----------------------->| |
21 | Controller | I0[3:0] | Flash memory |
22 | SPI/QSPI |<======================>| (SPI/QSPI) |
23 | | CLK | |
24 | |----------------------->| |
25 +------------+ +---------------+
26
27SF_DUAL_STACKED_FLASH:
28 - dual spi/qspi flash memories are connected with a single chipselect
29 line and these two memories are operating stacked fasion with shared buses.
30 - xilinx zynq qspi controller has implemented this feature [1]
31
32 +------------+ CS +---------------+
33 | |---------------------->| |
34 | | I0[3:0] | Upper Flash |
35 | | +=========>| memory |
36 | | | CLK | (SPI/QSPI) |
37 | | | +---->| |
38 | Controller | CS | | +---------------+
39 | SPI/QSPI |------------|----|---->| |
40 | | I0[3:0] | | | Lower Flash |
41 | |<===========+====|====>| memory |
42 | | CLK | | (SPI/QSPI) |
43 | |-----------------+---->| |
44 +------------+ +---------------+
45
46 - two memory flash devices should has same hw part attributes (like size,
47 vendor..etc)
48 - Configurations:
49 on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
50 Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
51 Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
52 - Operation:
53 accessing memories serially like one after another.
54 by default, if U_PAGE is unset lower memory should accessible,
55 once user wants to access upper memory need to set U_PAGE.
56
57SPI_FLASH_CONN_DUALPARALLEL:
58 - dual spi/qspi flash memories are connected with a single chipselect
59 line and these two memories are operating parallel with separate buses.
60 - xilinx zynq qspi controller has implemented this feature [1]
61
62 +-------------+ CS +---------------+
63 | |---------------------->| |
64 | | I0[3:0] | Upper Flash |
65 | |<=====================>| memory |
66 | | CLK | (SPI/QSPI) |
67 | |---------------------->| |
68 | Controller | CS +---------------+
69 | SPI/QSPI |---------------------->| |
70 | | I0[3:0] | Lower Flash |
71 | |<=====================>| memory |
72 | | CLK | (SPI/QSPI) |
73 | |---------------------->| |
74 +-------------+ +---------------+
75
76 - two memory flash devices should has same hw part attributes (like size,
77 vendor..etc)
78 - Configurations:
79 Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
80 - Operation:
81 Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
82 and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
83
84Note: Technically there is only one CS line from the controller, but
85zynq qspi controller has an internal hw logic to enable additional CS
86when controller is configured for dual memories.
87
88[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
89
90--
91Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
9205-01-2014.
93
README.ftssp010_spi_test
1SPI Flash test on Faraday A369 EVB:
2==================================
3
4U-Boot 2014.01-rc2-g3444b6f (Dec 20 2013 - 10:58:40)
5
6CPU: FA626TE 528 MHz
7AHB: 132 MHz
8APB: 66 MHz
9I2C: ready
10DRAM: 256 MiB
11MMU: on
12NAND: 512 MiB
13MMC: ftsdc010: 0
14*** Warning - bad CRC, using default environment
15
16In: serial
17Out: serial
18Err: serial
19Net: FTGMAC100#0
20Hit any key to stop autoboot: 0
21=> sf probe 0:0
22SF: Detected MX25L1605D with page size 256 Bytes, erase size 64 KiB, total 2 MiB
23=> sf read 0x10800000 0 0x400
24SF: 1024 bytes @ 0x0 Read: OK
25=> md 0x10800000
2610800000: ea000013 e59ff014 e59ff014 e59ff014 ................
2710800010: e59ff014 e59ff014 e59ff014 e59ff014 ................
2810800020: 1ff7b0c0 1ff7b120 1ff7b180 1ff7b1e0 .... ...........
2910800030: 1ff7b240 1ff7b2a0 1ff7b300 deadbeef @...............
3010800040: 10800000 0002c1f0 0007409c 00032048 .........@..H ..
3110800050: 1fd6af40 e10f0000 e3c0001f e38000d3 @...............
3210800060: e129f000 eb000001 eb000223 e12fff1e ..).....#...../.
3310800070: e3a00000 ee070f1e ee080f17 ee070f15 ................
3410800080: ee070f9a ee110f10 e3c00c03 e3c00087 ................
3510800090: e3c00a02 e3800002 e3800a01 ee010f10 ................
36108000a0: e1a0c00e eb007a68 e1a0e00c e1a0f00e ....hz..........
37108000b0: e1a00000 e1a00000 e1a00000 e1a00000 ................
38108000c0: e51fd078 e58de000 e14fe000 e58de004 x.........O.....
39108000d0: e3a0d013 e169f00d e1a0e00f e1b0f00e ......i.........
40108000e0: e24dd048 e88d1fff e51f20a0 e892000c H.M...... ......
41108000f0: e28d0048 e28d5034 e1a0100e e885000f H...4P..........
42
README.sandbox-spi
1Sandbox SPI/SPI Flash Implementation
2====================================
3
4U-Boot supports SPI and SPI flash emulation in sandbox. This must be enabled
5using the --spi_sf paramter when starting U-Boot.
6
7For example:
8
9$ make O=sandbox sandbox_config
10$ make O=sandbox
11$ ./sandbox/u-boot --spi_sf 0:0:W25Q128:b/chromeos_peach/out/image.bin
12
13The four parameters to spi_sf are:
14
15 SPI bus number (typically 0)
16 SPI chip select number (typically 0)
17 SPI chip to emulate
18 File containing emulated data
19
20Supported chips are W25Q16 (2MB), W25Q32 (4MB) and W25Q128 (16MB). Once
21U-Boot it started you can use 'sf' commands as normal. For example:
22
23$ ./b/sandbox/u-boot --spi_sf 0:0:W25Q128:b/chromeos_peach/out/image.bin \
24 -c "sf probe; sf test 0 100000; sf read 0 1000 1000; \
25 sf erase 1000 1000; sf write 0 1000 1000"
26
27
28U-Boot 2013.10-00237-gd4e0fdb (Nov 07 2013 - 20:08:15)
29
30DRAM: 128 MiB
31Using default environment
32
33In: serial
34Out: serial
35Err: serial
36SF: Detected W25Q128BV with page size 256 Bytes, erase size 4 KiB, total 16 MiB
37SPI flash test:
380 erase: 1 ticks, 1024000 KiB/s 8192.000 Mbps
391 check: 2 ticks, 512000 KiB/s 4096.000 Mbps
402 write: 6 ticks, 170666 KiB/s 1365.328 Mbps
413 read: 0 ticks, 1048576000 KiB/s -201326.-592 Mbps
42Test passed
430 erase: 1 ticks, 1024000 KiB/s 8192.000 Mbps
441 check: 2 ticks, 512000 KiB/s 4096.000 Mbps
452 write: 6 ticks, 170666 KiB/s 1365.328 Mbps
463 read: 0 ticks, 1048576000 KiB/s -201326.-592 Mbps
47SF: 4096 bytes @ 0x1000 Read: OK
48SF: 4096 bytes @ 0x1000 Erased: OK
49SF: 4096 bytes @ 0x1000 Written: OK
50
51
52Since the SPI bus is fully implemented as well as the SPI flash connected to
53it, you can also use low-level SPI commands to access the flash. For example
54this reads the device ID from the emulated chip:
55
56=> sspi 0 32 9f
57FFEF4018
58
59
60Simon Glass
61sjg@chromium.org
627/11/2013
63Note that the sandbox SPI implementation was written by Mike Frysinger
64<vapier@gentoo.org>.
65
README.sh_qspi_test
1-------------------------------------------------
2 Simple steps used to test the SH-QSPI at U-Boot
3-------------------------------------------------
4
5#0, Currently, SH-QSPI is used by lager board (Renesas ARM SoC R8A7790)
6 and koelsch board (Renesas ARM SoC R8A7791). These boot from SPI ROM
7 basically. Thus, U-Boot start, SH-QSPI will is operating normally.
8
9#1, build U-Boot and load u-boot.bin
10
11 => tftpboot 40000000 u-boot.bin
12 sh_eth Waiting for PHY auto negotiation to complete.. done
13 sh_eth: 100Base/Half
14 Using sh_eth device
15 TFTP from server 192.168.169.1; our IP address is 192.168.169.79
16 Filename 'u-boot.bin'.
17 Load address: 0x40000000
18 Loading: ############
19 2.5 MiB/s
20 done
21 Bytes transferred = 175364 (2ad04 hex)
22
23#2, Commands to erase/write u-boot to flash device
24
25 Note: This method is description of the lager board. If you want to use the
26 other boards, please change the value according to each environment.
27
28 => sf probe 0
29 SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 64 KiB, total 64 MiB
30 => sf erase 80000 40000
31 SF: 262144 bytes @ 0x80000 Erased: OK
32 => sf write 40000000 80000 175364
33 SF: 1528676 bytes @ 0x80000 Written: OK
34 =>
35
36#3, Push reset button.
37
38 If you're written correctly and driver works properly, U-Boot starts.
39
README.ti_qspi_am43x_test
1Testing details-
2----------------
3
4This doc simply illustrated the testing details of qspi flash
5driver with Macronix M25L51235 flash device.
6
7The test includes
8- probing the flash device
9- erasing the flash device
10- Writing to flash
11- Reading the contents of the flash.
12
13Test Log
14--------
15
16Hit any key to stop autoboot: 0
17U-Boot# sf probe 0
18SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000
19U-Boot# sf erase 0 0x80000
20SF: 524288 bytes @ 0x0 Erased: OK
21U-Boot# mw 81000000 0xdededede 0x40000
22U-Boot# sf write 81000000 0 0x40000
23SF: 262144 bytes @ 0x0 Written: OK
24U-Boot# sf read 82000000 0 0x40000
25SF: 262144 bytes @ 0x0 Read: OK
26U-Boot# md 0x82000000
2782000000: dededede dededede dededede dededede ................
2882000010: dededede dededede dededede dededede ................
2982000020: dededede dededede dededede dededede ................
3082000030: dededede dededede dededede dededede ................
3182000040: dededede dededede dededede dededede ................
3282000050: dededede dededede dededede dededede ................
3382000060: dededede dededede dededede dededede ................
3482000070: dededede dededede dededede dededede ................
3582000080: dededede dededede dededede dededede ................
3682000090: dededede dededede dededede dededede ................
37820000a0: dededede dededede dededede dededede ................
38820000b0: dededede dededede dededede dededede ................
39820000c0: dededede dededede dededede dededede ................
40820000d0: dededede dededede dededede dededede ................
41820000e0: dededede dededede dededede dededede ................
42820000f0: dededede dededede dededede dededede ................
43U-Boot# md 0x82010000
4482010000: dededede dededede dededede dededede ................
4582010010: dededede dededede dededede dededede ................
4682010020: dededede dededede dededede dededede ................
4782010030: dededede dededede dededede dededede ................
4882010040: dededede dededede dededede dededede ................
4982010050: dededede dededede dededede dededede ................
5082010060: dededede dededede dededede dededede ................
5182010070: dededede dededede dededede dededede ................
5282010080: dededede dededede dededede dededede ................
5382010090: dededede dededede dededede dededede ................
54820100a0: dededede dededede dededede dededede ................
55820100b0: dededede dededede dededede dededede ................
56820100c0: dededede dededede dededede dededede ................
57820100d0: dededede dededede dededede dededede ................
58820100e0: dededede dededede dededede dededede ................
59820100f0: dededede dededede dededede dededede ................
60U-Boot# md 0x82030000
6182030000: dededede dededede dededede dededede ................
6282030010: dededede dededede dededede dededede ................
6382030020: dededede dededede dededede dededede ................
6482030030: dededede dededede dededede dededede ................
6582030040: dededede dededede dededede dededede ................
6682030050: dededede dededede dededede dededede ................
6782030060: dededede dededede dededede dededede ................
6882030070: dededede dededede dededede dededede ................
6982030080: dededede dededede dededede dededede ................
7082030090: dededede dededede dededede dededede ................
71820300a0: dededede dededede dededede dededede ................
72820300b0: dededede dededede dededede dededede ................
73820300c0: dededede dededede dededede dededede ................
74820300d0: dededede dededede dededede dededede ................
75820300e0: dededede dededede dededede dededede ................
76820300f0: dededede dededede dededede dededede ................
77
README.ti_qspi_dra_test
1-------------------------------------------------
2 Simple steps used to test the QSPI at U-Boot
3-------------------------------------------------
4
5For #1, build the patched U-Boot and load MLO/u-boot.img
6
7----------------------------------
8Boot from another medium like MMC
9----------------------------------
10
11U-Boot# mmc dev 0
12mmc0 is current device
13U-Boot# fatload mmc 0 0x82000000 MLO
14reading MLO
1555872 bytes read in 8 ms (6.7 MiB/s)
16U-Boot# fatload mmc 0 0x83000000 u-boot.img
17reading u-boot.img
18248600 bytes read in 19 ms (12.5 MiB/s)
19
20--------------------------------------------------
21Commands to erase/write u-boot/mlo to flash device
22--------------------------------------------------
23U-Boot# sf probe 0
24SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c000000
25SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR
26U-Boot# sf erase 0 0x10000
27SF: 65536 bytes @ 0x0 Erased: OK
28U-Boot# sf erase 0x20000 0x10000
29SF: 65536 bytes @ 0x20000 Erased: OK
30U-Boot# sf erase 0x30000 0x10000
31SF: 65536 bytes @ 0x30000 Erased: OK
32U-Boot# sf erase 0x40000 0x10000
33SF: 65536 bytes @ 0x40000 Erased: OK
34U-Boot# sf erase 0x50000 0x10000
35SF: 65536 bytes @ 0x50000 Erased: OK
36U-Boot# sf erase 0x60000 0x10000
37SF: 65536 bytes @ 0x60000 Erased: OK
38U-Boot# sf write 82000000 0 0x10000
39SF: 65536 bytes @ 0x0 Written: OK
40U-Boot# sf write 83000000 0x20000 0x60000
41SF: 393216 bytes @ 0x20000 Written: OK
42
43For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power
44on. ROM should find the GP header at offset 0 and load/execute SPL. SPL
45then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to
46find a U-Boot image header at offset 0x20000 (set in the config file)
47and proceeds to load that image using the U-Boot image payload offset/size
48from the header. It will then start U-Boot.
49
README.ti_qspi_flash
1QSPI U-Boot support
2------------------
3
4Host processor is connected to serial flash device via qpsi
5interface. QSPI is a kind of spi module that allows single,
6dual and quad read access to external spi devices. The module
7has a memory mapped interface which provide direct interface
8for accessing data form external spi devices.
9
10The one QSPI in the device is primarily intended for fast booting
11from Quad SPI flash devices.
12
13Usecase
14-------
15
16MLO/u-boot.img will be flashed from SD/MMC to the flash device
17using serial flash erase and write commands. Then, switch settings
18will be changed to qspi boot. Then, the ROM code will read MLO
19from the predefined location in the flash, where it was flashed and
20execute it after storing it in SDRAM. Then, the MLO will read
21u-boot.img from flash and execute it from SDRAM.
22
23SPI mode
24-------
25SPI mode uses mtd spi framework for transfer and reception of data.
26Can be used in:
271. Normal mode: use single pin for transfers
282. Dual Mode: use two pins for transfers.
293. Quad mode: use four pin for transfer
30
31Memory mapped read mode
32-----------------------
33In this, SPI controller is configured using configuration port and then
34controller is switched to memory mapped port for data read.
35
36Driver
37------
38drivers/qspi/ti_qspi.c
39 - Newly created file which is responsible for configuring the
40 qspi controller and also for providing the low level api which
41 is responsible for transferring the datas from host controller
42 to flash device and vice versa.
43
44Testing
45-------
46A seperated file named README.dra_qspi_test has been created which gives all the
47details about the commands required to test qspi at U-Boot level.
48