1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Ethernet driver for TI K2HK EVM.
4 *
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
7 */
8 #include <common.h>
9 #include <command.h>
10 #include <console.h>
11
12 #include <dm.h>
13 #include <dm/lists.h>
14
15 #include <net.h>
16 #include <phy.h>
17 #include <errno.h>
18 #include <miiphy.h>
19 #include <malloc.h>
20 #include <asm/ti-common/keystone_nav.h>
21 #include <asm/ti-common/keystone_net.h>
22 #include <asm/ti-common/keystone_serdes.h>
23 #include <asm/arch/psc_defs.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #ifndef CONFIG_DM_ETH
28 unsigned int emac_open;
29 static struct mii_dev *mdio_bus;
30 static unsigned int sys_has_mdio = 1;
31 #endif
32
33 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
34 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
35 #else
36 #define emac_gigabit_enable(x) /* no gigabit to enable */
37 #endif
38
39 #define RX_BUFF_NUMS 24
40 #define RX_BUFF_LEN 1520
41 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
42 #define SGMII_ANEG_TIMEOUT 4000
43
44 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
45
46 #ifndef CONFIG_DM_ETH
47 struct rx_buff_desc net_rx_buffs = {
48 .buff_ptr = rx_buffs,
49 .num_buffs = RX_BUFF_NUMS,
50 .buff_len = RX_BUFF_LEN,
51 .rx_flow = 22,
52 };
53 #endif
54
55 #ifdef CONFIG_DM_ETH
56
57 enum link_type {
58 LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
59 LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
60 LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
61 LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
62 LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
63 LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
64 LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
65 LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
66 LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
67 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
68 };
69
70 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
71 ((mac)[2] << 16) | ((mac)[3] << 24))
72 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
73
74 #ifdef CONFIG_KSNET_NETCP_V1_0
75
76 #define EMAC_EMACSW_BASE_OFS 0x90800
77 #define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
78
79 /* CPSW Switch slave registers */
80 #define CPGMACSL_REG_SA_LO 0x10
81 #define CPGMACSL_REG_SA_HI 0x14
82
83 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
84 (x) * 0x30)
85
86 #elif defined CONFIG_KSNET_NETCP_V1_5
87
88 #define EMAC_EMACSW_PORT_BASE_OFS 0x222000
89
90 /* CPSW Switch slave registers */
91 #define CPGMACSL_REG_SA_LO 0x308
92 #define CPGMACSL_REG_SA_HI 0x30c
93
94 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
95 (x) * 0x1000)
96
97 #endif
98
99
100 struct ks2_eth_priv {
101 struct udevice *dev;
102 struct phy_device *phydev;
103 struct mii_dev *mdio_bus;
104 int phy_addr;
105 phy_interface_t phy_if;
106 int sgmii_link_type;
107 void *mdio_base;
108 struct rx_buff_desc net_rx_buffs;
109 struct pktdma_cfg *netcp_pktdma;
110 void *hd;
111 int slave_port;
112 enum link_type link_type;
113 bool emac_open;
114 bool has_mdio;
115 };
116 #endif
117
118 /* MDIO */
119
keystone2_mdio_reset(struct mii_dev * bus)120 static int keystone2_mdio_reset(struct mii_dev *bus)
121 {
122 u_int32_t clkdiv;
123 struct mdio_regs *adap_mdio = bus->priv;
124
125 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
126
127 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
128 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
129 &adap_mdio->control);
130
131 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
132 ;
133
134 return 0;
135 }
136
137 /**
138 * keystone2_mdio_read - read a PHY register via MDIO interface.
139 * Blocks until operation is complete.
140 */
keystone2_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)141 static int keystone2_mdio_read(struct mii_dev *bus,
142 int addr, int devad, int reg)
143 {
144 int tmp;
145 struct mdio_regs *adap_mdio = bus->priv;
146
147 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
148 ;
149
150 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
151 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
152 &adap_mdio->useraccess0);
153
154 /* Wait for command to complete */
155 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
156 ;
157
158 if (tmp & MDIO_USERACCESS0_ACK)
159 return tmp & 0xffff;
160
161 return -1;
162 }
163
164 /**
165 * keystone2_mdio_write - write to a PHY register via MDIO interface.
166 * Blocks until operation is complete.
167 */
keystone2_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)168 static int keystone2_mdio_write(struct mii_dev *bus,
169 int addr, int devad, int reg, u16 val)
170 {
171 struct mdio_regs *adap_mdio = bus->priv;
172
173 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
174 ;
175
176 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
177 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
178 (val & 0xffff), &adap_mdio->useraccess0);
179
180 /* Wait for command to complete */
181 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
182 ;
183
184 return 0;
185 }
186
187 #ifndef CONFIG_DM_ETH
188 static void __attribute__((unused))
keystone2_eth_gigabit_enable(struct eth_device * dev)189 keystone2_eth_gigabit_enable(struct eth_device *dev)
190 {
191 u_int16_t data;
192 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
193
194 if (sys_has_mdio) {
195 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
196 MDIO_DEVAD_NONE, 0);
197 /* speed selection MSB */
198 if (!(data & (1 << 6)))
199 return;
200 }
201
202 /*
203 * Check if link detected is giga-bit
204 * If Gigabit mode detected, enable gigbit in MAC
205 */
206 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
207 CPGMACSL_REG_CTL) |
208 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
209 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
210 }
211 #else
212 static void __attribute__((unused))
keystone2_eth_gigabit_enable(struct udevice * dev)213 keystone2_eth_gigabit_enable(struct udevice *dev)
214 {
215 struct ks2_eth_priv *priv = dev_get_priv(dev);
216 u_int16_t data;
217
218 if (priv->has_mdio) {
219 data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr,
220 MDIO_DEVAD_NONE, 0);
221 /* speed selection MSB */
222 if (!(data & (1 << 6)))
223 return;
224 }
225
226 /*
227 * Check if link detected is giga-bit
228 * If Gigabit mode detected, enable gigbit in MAC
229 */
230 writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
231 CPGMACSL_REG_CTL) |
232 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
233 DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
234 }
235 #endif
236
237 #ifdef CONFIG_SOC_K2G
keystone_rgmii_config(struct phy_device * phy_dev)238 int keystone_rgmii_config(struct phy_device *phy_dev)
239 {
240 unsigned int i, status;
241
242 i = 0;
243 do {
244 if (i > SGMII_ANEG_TIMEOUT) {
245 puts(" TIMEOUT !\n");
246 phy_dev->link = 0;
247 return 0;
248 }
249
250 if (ctrlc()) {
251 puts("user interrupt!\n");
252 phy_dev->link = 0;
253 return -EINTR;
254 }
255
256 if ((i++ % 500) == 0)
257 printf(".");
258
259 udelay(1000); /* 1 ms */
260 status = readl(RGMII_STATUS_REG);
261 } while (!(status & RGMII_REG_STATUS_LINK));
262
263 puts(" done\n");
264
265 return 0;
266 }
267 #else
keystone_sgmii_config(struct phy_device * phy_dev,int port,int interface)268 int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
269 {
270 unsigned int i, status, mask;
271 unsigned int mr_adv_ability, control;
272
273 switch (interface) {
274 case SGMII_LINK_MAC_MAC_AUTONEG:
275 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
276 SGMII_REG_MR_ADV_LINK |
277 SGMII_REG_MR_ADV_FULL_DUPLEX |
278 SGMII_REG_MR_ADV_GIG_MODE);
279 control = (SGMII_REG_CONTROL_MASTER |
280 SGMII_REG_CONTROL_AUTONEG);
281
282 break;
283 case SGMII_LINK_MAC_PHY:
284 case SGMII_LINK_MAC_PHY_FORCED:
285 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
286 control = SGMII_REG_CONTROL_AUTONEG;
287
288 break;
289 case SGMII_LINK_MAC_MAC_FORCED:
290 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
291 SGMII_REG_MR_ADV_LINK |
292 SGMII_REG_MR_ADV_FULL_DUPLEX |
293 SGMII_REG_MR_ADV_GIG_MODE);
294 control = SGMII_REG_CONTROL_MASTER;
295
296 break;
297 case SGMII_LINK_MAC_FIBER:
298 mr_adv_ability = 0x20;
299 control = SGMII_REG_CONTROL_AUTONEG;
300
301 break;
302 default:
303 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
304 control = SGMII_REG_CONTROL_AUTONEG;
305 }
306
307 __raw_writel(0, SGMII_CTL_REG(port));
308
309 /*
310 * Wait for the SerDes pll to lock,
311 * but don't trap if lock is never read
312 */
313 for (i = 0; i < 1000; i++) {
314 udelay(2000);
315 status = __raw_readl(SGMII_STATUS_REG(port));
316 if ((status & SGMII_REG_STATUS_LOCK) != 0)
317 break;
318 }
319
320 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
321 __raw_writel(control, SGMII_CTL_REG(port));
322
323
324 mask = SGMII_REG_STATUS_LINK;
325
326 if (control & SGMII_REG_CONTROL_AUTONEG)
327 mask |= SGMII_REG_STATUS_AUTONEG;
328
329 status = __raw_readl(SGMII_STATUS_REG(port));
330 if ((status & mask) == mask)
331 return 0;
332
333 printf("\n%s Waiting for SGMII auto negotiation to complete",
334 phy_dev->dev->name);
335 while ((status & mask) != mask) {
336 /*
337 * Timeout reached ?
338 */
339 if (i > SGMII_ANEG_TIMEOUT) {
340 puts(" TIMEOUT !\n");
341 phy_dev->link = 0;
342 return 0;
343 }
344
345 if (ctrlc()) {
346 puts("user interrupt!\n");
347 phy_dev->link = 0;
348 return -EINTR;
349 }
350
351 if ((i++ % 500) == 0)
352 printf(".");
353
354 udelay(1000); /* 1 ms */
355 status = __raw_readl(SGMII_STATUS_REG(port));
356 }
357 puts(" done\n");
358
359 return 0;
360 }
361 #endif
362
mac_sl_reset(u32 port)363 int mac_sl_reset(u32 port)
364 {
365 u32 i, v;
366
367 if (port >= DEVICE_N_GMACSL_PORTS)
368 return GMACSL_RET_INVALID_PORT;
369
370 /* Set the soft reset bit */
371 writel(CPGMAC_REG_RESET_VAL_RESET,
372 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
373
374 /* Wait for the bit to clear */
375 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
376 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
377 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
378 CPGMAC_REG_RESET_VAL_RESET)
379 return GMACSL_RET_OK;
380 }
381
382 /* Timeout on the reset */
383 return GMACSL_RET_WARN_RESET_INCOMPLETE;
384 }
385
mac_sl_config(u_int16_t port,struct mac_sl_cfg * cfg)386 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
387 {
388 u32 v, i;
389 int ret = GMACSL_RET_OK;
390
391 if (port >= DEVICE_N_GMACSL_PORTS)
392 return GMACSL_RET_INVALID_PORT;
393
394 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
395 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
396 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
397 }
398
399 /* Must wait if the device is undergoing reset */
400 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
401 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
402 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
403 CPGMAC_REG_RESET_VAL_RESET)
404 break;
405 }
406
407 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
408 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
409
410 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
411 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
412
413 #ifndef CONFIG_SOC_K2HK
414 /* Map RX packet flow priority to 0 */
415 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
416 #endif
417
418 return ret;
419 }
420
ethss_config(u32 ctl,u32 max_pkt_size)421 int ethss_config(u32 ctl, u32 max_pkt_size)
422 {
423 u32 i;
424
425 /* Max length register */
426 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
427
428 /* Control register */
429 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
430
431 /* All statistics enabled by default */
432 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
433 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
434
435 /* Reset and enable the ALE */
436 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
437 CPSW_REG_VAL_ALE_CTL_BYPASS,
438 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
439
440 /* All ports put into forward mode */
441 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
442 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
443 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
444
445 return 0;
446 }
447
ethss_start(void)448 int ethss_start(void)
449 {
450 int i;
451 struct mac_sl_cfg cfg;
452
453 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
454 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
455
456 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
457 mac_sl_reset(i);
458 mac_sl_config(i, &cfg);
459 }
460
461 return 0;
462 }
463
ethss_stop(void)464 int ethss_stop(void)
465 {
466 int i;
467
468 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
469 mac_sl_reset(i);
470
471 return 0;
472 }
473
474 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
475 .clk = SERDES_CLOCK_156P25M,
476 .rate = SERDES_RATE_5G,
477 .rate_mode = SERDES_QUARTER_RATE,
478 .intf = SERDES_PHY_SGMII,
479 .loopback = 0,
480 };
481
482 #ifndef CONFIG_SOC_K2G
keystone2_net_serdes_setup(void)483 static void keystone2_net_serdes_setup(void)
484 {
485 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
486 &ks2_serdes_sgmii_156p25mhz,
487 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
488
489 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
490 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
491 &ks2_serdes_sgmii_156p25mhz,
492 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
493 #endif
494
495 /* wait till setup */
496 udelay(5000);
497 }
498 #endif
499
500 #ifndef CONFIG_DM_ETH
501
keystone2_eth_read_mac_addr(struct eth_device * dev)502 int keystone2_eth_read_mac_addr(struct eth_device *dev)
503 {
504 struct eth_priv_t *eth_priv;
505 u32 maca = 0;
506 u32 macb = 0;
507
508 eth_priv = (struct eth_priv_t *)dev->priv;
509
510 /* Read the e-fuse mac address */
511 if (eth_priv->slave_port == 1) {
512 maca = __raw_readl(MAC_ID_BASE_ADDR);
513 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
514 }
515
516 dev->enetaddr[0] = (macb >> 8) & 0xff;
517 dev->enetaddr[1] = (macb >> 0) & 0xff;
518 dev->enetaddr[2] = (maca >> 24) & 0xff;
519 dev->enetaddr[3] = (maca >> 16) & 0xff;
520 dev->enetaddr[4] = (maca >> 8) & 0xff;
521 dev->enetaddr[5] = (maca >> 0) & 0xff;
522
523 return 0;
524 }
525
cpmac_drv_send(u32 * buffer,int num_bytes,int slave_port_num)526 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
527 {
528 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
529 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
530
531 return ksnav_send(&netcp_pktdma, buffer,
532 num_bytes, (slave_port_num) << 16);
533 }
534
535 /* Eth device open */
keystone2_eth_open(struct eth_device * dev,bd_t * bis)536 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
537 {
538 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
539 struct phy_device *phy_dev = eth_priv->phy_dev;
540
541 debug("+ emac_open\n");
542
543 net_rx_buffs.rx_flow = eth_priv->rx_flow;
544
545 sys_has_mdio =
546 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
547
548 if (sys_has_mdio)
549 keystone2_mdio_reset(mdio_bus);
550
551 #ifdef CONFIG_SOC_K2G
552 keystone_rgmii_config(phy_dev);
553 #else
554 keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
555 eth_priv->sgmii_link_type);
556 #endif
557
558 udelay(10000);
559
560 /* On chip switch configuration */
561 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
562
563 /* TODO: add error handling code */
564 if (qm_init()) {
565 printf("ERROR: qm_init()\n");
566 return -1;
567 }
568 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
569 qm_close();
570 printf("ERROR: netcp_init()\n");
571 return -1;
572 }
573
574 /*
575 * Streaming switch configuration. If not present this
576 * statement is defined to void in target.h.
577 * If present this is usually defined to a series of register writes
578 */
579 hw_config_streaming_switch();
580
581 if (sys_has_mdio) {
582 keystone2_mdio_reset(mdio_bus);
583
584 phy_startup(phy_dev);
585 if (phy_dev->link == 0) {
586 ksnav_close(&netcp_pktdma);
587 qm_close();
588 return -1;
589 }
590 }
591
592 emac_gigabit_enable(dev);
593
594 ethss_start();
595
596 debug("- emac_open\n");
597
598 emac_open = 1;
599
600 return 0;
601 }
602
603 /* Eth device close */
keystone2_eth_close(struct eth_device * dev)604 void keystone2_eth_close(struct eth_device *dev)
605 {
606 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
607 struct phy_device *phy_dev = eth_priv->phy_dev;
608
609 debug("+ emac_close\n");
610
611 if (!emac_open)
612 return;
613
614 ethss_stop();
615
616 ksnav_close(&netcp_pktdma);
617 qm_close();
618 phy_shutdown(phy_dev);
619
620 emac_open = 0;
621
622 debug("- emac_close\n");
623 }
624
625 /*
626 * This function sends a single packet on the network and returns
627 * positive number (number of bytes transmitted) or negative for error
628 */
keystone2_eth_send_packet(struct eth_device * dev,void * packet,int length)629 static int keystone2_eth_send_packet(struct eth_device *dev,
630 void *packet, int length)
631 {
632 int ret_status = -1;
633 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
634 struct phy_device *phy_dev = eth_priv->phy_dev;
635
636 genphy_update_link(phy_dev);
637 if (phy_dev->link == 0)
638 return -1;
639
640 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
641 return ret_status;
642
643 return length;
644 }
645
646 /*
647 * This function handles receipt of a packet from the network
648 */
keystone2_eth_rcv_packet(struct eth_device * dev)649 static int keystone2_eth_rcv_packet(struct eth_device *dev)
650 {
651 void *hd;
652 int pkt_size;
653 u32 *pkt;
654
655 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
656 if (hd == NULL)
657 return 0;
658
659 net_process_received_packet((uchar *)pkt, pkt_size);
660
661 ksnav_release_rxhd(&netcp_pktdma, hd);
662
663 return pkt_size;
664 }
665
666 #ifdef CONFIG_MCAST_TFTP
keystone2_eth_bcast_addr(struct eth_device * dev,u32 ip,u8 set)667 static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set)
668 {
669 return 0;
670 }
671 #endif
672
673 /*
674 * This function initializes the EMAC hardware.
675 */
keystone2_emac_initialize(struct eth_priv_t * eth_priv)676 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
677 {
678 int res;
679 struct eth_device *dev;
680 struct phy_device *phy_dev;
681 struct mdio_regs *adap_mdio = (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
682
683 dev = malloc(sizeof(struct eth_device));
684 if (dev == NULL)
685 return -1;
686
687 memset(dev, 0, sizeof(struct eth_device));
688
689 strcpy(dev->name, eth_priv->int_name);
690 dev->priv = eth_priv;
691
692 keystone2_eth_read_mac_addr(dev);
693
694 dev->iobase = 0;
695 dev->init = keystone2_eth_open;
696 dev->halt = keystone2_eth_close;
697 dev->send = keystone2_eth_send_packet;
698 dev->recv = keystone2_eth_rcv_packet;
699 #ifdef CONFIG_MCAST_TFTP
700 dev->mcast = keystone2_eth_bcast_addr;
701 #endif
702
703 eth_register(dev);
704
705 /* Register MDIO bus if it's not registered yet */
706 if (!mdio_bus) {
707 mdio_bus = mdio_alloc();
708 mdio_bus->read = keystone2_mdio_read;
709 mdio_bus->write = keystone2_mdio_write;
710 mdio_bus->reset = keystone2_mdio_reset;
711 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
712 strcpy(mdio_bus->name, "ethernet-mdio");
713
714 res = mdio_register(mdio_bus);
715 if (res)
716 return res;
717 }
718
719 #ifndef CONFIG_SOC_K2G
720 keystone2_net_serdes_setup();
721 #endif
722
723 /* Create phy device and bind it with driver */
724 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
725 phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
726 dev, eth_priv->phy_if);
727 phy_config(phy_dev);
728 #else
729 phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
730 eth_priv->phy_if);
731 phy_dev->dev = dev;
732 #endif
733 eth_priv->phy_dev = phy_dev;
734
735 return 0;
736 }
737
738 #else
739
ks2_eth_start(struct udevice * dev)740 static int ks2_eth_start(struct udevice *dev)
741 {
742 struct ks2_eth_priv *priv = dev_get_priv(dev);
743
744 #ifdef CONFIG_SOC_K2G
745 keystone_rgmii_config(priv->phydev);
746 #else
747 keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
748 priv->sgmii_link_type);
749 #endif
750
751 udelay(10000);
752
753 /* On chip switch configuration */
754 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
755
756 qm_init();
757
758 if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
759 pr_err("ksnav_init failed\n");
760 goto err_knav_init;
761 }
762
763 /*
764 * Streaming switch configuration. If not present this
765 * statement is defined to void in target.h.
766 * If present this is usually defined to a series of register writes
767 */
768 hw_config_streaming_switch();
769
770 if (priv->has_mdio) {
771 keystone2_mdio_reset(priv->mdio_bus);
772
773 phy_startup(priv->phydev);
774 if (priv->phydev->link == 0) {
775 pr_err("phy startup failed\n");
776 goto err_phy_start;
777 }
778 }
779
780 emac_gigabit_enable(dev);
781
782 ethss_start();
783
784 priv->emac_open = true;
785
786 return 0;
787
788 err_phy_start:
789 ksnav_close(priv->netcp_pktdma);
790 err_knav_init:
791 qm_close();
792
793 return -EFAULT;
794 }
795
ks2_eth_send(struct udevice * dev,void * packet,int length)796 static int ks2_eth_send(struct udevice *dev, void *packet, int length)
797 {
798 struct ks2_eth_priv *priv = dev_get_priv(dev);
799
800 genphy_update_link(priv->phydev);
801 if (priv->phydev->link == 0)
802 return -1;
803
804 if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
805 length = EMAC_MIN_ETHERNET_PKT_SIZE;
806
807 return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
808 length, (priv->slave_port) << 16);
809 }
810
ks2_eth_recv(struct udevice * dev,int flags,uchar ** packetp)811 static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
812 {
813 struct ks2_eth_priv *priv = dev_get_priv(dev);
814 int pkt_size;
815 u32 *pkt = NULL;
816
817 priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
818 if (priv->hd == NULL)
819 return -EAGAIN;
820
821 *packetp = (uchar *)pkt;
822
823 return pkt_size;
824 }
825
ks2_eth_free_pkt(struct udevice * dev,uchar * packet,int length)826 static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
827 int length)
828 {
829 struct ks2_eth_priv *priv = dev_get_priv(dev);
830
831 ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
832
833 return 0;
834 }
835
ks2_eth_stop(struct udevice * dev)836 static void ks2_eth_stop(struct udevice *dev)
837 {
838 struct ks2_eth_priv *priv = dev_get_priv(dev);
839
840 if (!priv->emac_open)
841 return;
842 ethss_stop();
843
844 ksnav_close(priv->netcp_pktdma);
845 qm_close();
846 phy_shutdown(priv->phydev);
847 priv->emac_open = false;
848 }
849
ks2_eth_read_rom_hwaddr(struct udevice * dev)850 int ks2_eth_read_rom_hwaddr(struct udevice *dev)
851 {
852 struct ks2_eth_priv *priv = dev_get_priv(dev);
853 struct eth_pdata *pdata = dev_get_platdata(dev);
854 u32 maca = 0;
855 u32 macb = 0;
856
857 /* Read the e-fuse mac address */
858 if (priv->slave_port == 1) {
859 maca = __raw_readl(MAC_ID_BASE_ADDR);
860 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
861 }
862
863 pdata->enetaddr[0] = (macb >> 8) & 0xff;
864 pdata->enetaddr[1] = (macb >> 0) & 0xff;
865 pdata->enetaddr[2] = (maca >> 24) & 0xff;
866 pdata->enetaddr[3] = (maca >> 16) & 0xff;
867 pdata->enetaddr[4] = (maca >> 8) & 0xff;
868 pdata->enetaddr[5] = (maca >> 0) & 0xff;
869
870 return 0;
871 }
872
ks2_eth_write_hwaddr(struct udevice * dev)873 int ks2_eth_write_hwaddr(struct udevice *dev)
874 {
875 struct ks2_eth_priv *priv = dev_get_priv(dev);
876 struct eth_pdata *pdata = dev_get_platdata(dev);
877
878 writel(mac_hi(pdata->enetaddr),
879 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
880 CPGMACSL_REG_SA_HI);
881 writel(mac_lo(pdata->enetaddr),
882 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
883 CPGMACSL_REG_SA_LO);
884
885 return 0;
886 }
887
ks2_eth_probe(struct udevice * dev)888 static int ks2_eth_probe(struct udevice *dev)
889 {
890 struct ks2_eth_priv *priv = dev_get_priv(dev);
891 struct mii_dev *mdio_bus;
892 int ret;
893
894 priv->dev = dev;
895
896 /* These clock enables has to be moved to common location */
897 if (cpu_is_k2g())
898 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
899
900 /* By default, select PA PLL clock as PA clock source */
901 #ifndef CONFIG_SOC_K2G
902 if (psc_enable_module(KS2_LPSC_PA))
903 return -EACCES;
904 #endif
905 if (psc_enable_module(KS2_LPSC_CPGMAC))
906 return -EACCES;
907 if (psc_enable_module(KS2_LPSC_CRYPTO))
908 return -EACCES;
909
910 if (cpu_is_k2e() || cpu_is_k2l())
911 pll_pa_clk_sel();
912
913
914 priv->net_rx_buffs.buff_ptr = rx_buffs;
915 priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
916 priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
917
918 if (priv->slave_port == 1) {
919 /*
920 * Register MDIO bus for slave 0 only, other slave have
921 * to re-use the same
922 */
923 mdio_bus = mdio_alloc();
924 if (!mdio_bus) {
925 pr_err("MDIO alloc failed\n");
926 return -ENOMEM;
927 }
928 priv->mdio_bus = mdio_bus;
929 mdio_bus->read = keystone2_mdio_read;
930 mdio_bus->write = keystone2_mdio_write;
931 mdio_bus->reset = keystone2_mdio_reset;
932 mdio_bus->priv = priv->mdio_base;
933 sprintf(mdio_bus->name, "ethernet-mdio");
934
935 ret = mdio_register(mdio_bus);
936 if (ret) {
937 pr_err("MDIO bus register failed\n");
938 return ret;
939 }
940 } else {
941 /* Get the MDIO bus from slave 0 device */
942 struct ks2_eth_priv *parent_priv;
943
944 parent_priv = dev_get_priv(dev->parent);
945 priv->mdio_bus = parent_priv->mdio_bus;
946 }
947
948 #ifndef CONFIG_SOC_K2G
949 keystone2_net_serdes_setup();
950 #endif
951
952 priv->netcp_pktdma = &netcp_pktdma;
953
954 if (priv->has_mdio) {
955 priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
956 dev, priv->phy_if);
957 phy_config(priv->phydev);
958 }
959
960 return 0;
961 }
962
ks2_eth_remove(struct udevice * dev)963 int ks2_eth_remove(struct udevice *dev)
964 {
965 struct ks2_eth_priv *priv = dev_get_priv(dev);
966
967 free(priv->phydev);
968 mdio_unregister(priv->mdio_bus);
969 mdio_free(priv->mdio_bus);
970
971 return 0;
972 }
973
974 static const struct eth_ops ks2_eth_ops = {
975 .start = ks2_eth_start,
976 .send = ks2_eth_send,
977 .recv = ks2_eth_recv,
978 .free_pkt = ks2_eth_free_pkt,
979 .stop = ks2_eth_stop,
980 .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
981 .write_hwaddr = ks2_eth_write_hwaddr,
982 };
983
ks2_eth_bind_slaves(struct udevice * dev,int gbe,int * gbe_0)984 static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
985 {
986 const void *fdt = gd->fdt_blob;
987 struct udevice *sl_dev;
988 int interfaces;
989 int sec_slave;
990 int slave;
991 int ret;
992 char *slave_name;
993
994 interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
995 fdt_for_each_subnode(slave, fdt, interfaces) {
996 int slave_no;
997
998 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
999 if (slave_no == -ENOENT)
1000 continue;
1001
1002 if (slave_no == 0) {
1003 /* This is the current eth device */
1004 *gbe_0 = slave;
1005 } else {
1006 /* Slave devices to be registered */
1007 slave_name = malloc(20);
1008 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
1009 ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
1010 slave_name, offset_to_ofnode(slave),
1011 &sl_dev);
1012 if (ret) {
1013 pr_err("ks2_net - not able to bind slave interfaces\n");
1014 return ret;
1015 }
1016 }
1017 }
1018
1019 sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
1020 fdt_for_each_subnode(slave, fdt, sec_slave) {
1021 int slave_no;
1022
1023 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
1024 if (slave_no == -ENOENT)
1025 continue;
1026
1027 /* Slave devices to be registered */
1028 slave_name = malloc(20);
1029 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
1030 ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
1031 offset_to_ofnode(slave), &sl_dev);
1032 if (ret) {
1033 pr_err("ks2_net - not able to bind slave interfaces\n");
1034 return ret;
1035 }
1036 }
1037
1038 return 0;
1039 }
1040
ks2_eth_parse_slave_interface(int netcp,int slave,struct ks2_eth_priv * priv,struct eth_pdata * pdata)1041 static int ks2_eth_parse_slave_interface(int netcp, int slave,
1042 struct ks2_eth_priv *priv,
1043 struct eth_pdata *pdata)
1044 {
1045 const void *fdt = gd->fdt_blob;
1046 int mdio;
1047 int phy;
1048 int dma_count;
1049 u32 dma_channel[8];
1050
1051 priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
1052 priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
1053
1054 /* U-Boot slave port number starts with 1 instead of 0 */
1055 priv->slave_port += 1;
1056
1057 dma_count = fdtdec_get_int_array_count(fdt, netcp,
1058 "ti,navigator-dmas",
1059 dma_channel, 8);
1060
1061 if (dma_count > (2 * priv->slave_port)) {
1062 int dma_idx;
1063
1064 dma_idx = priv->slave_port * 2 - 1;
1065 priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
1066 }
1067
1068 priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
1069
1070 phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
1071 if (phy >= 0) {
1072 priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
1073
1074 mdio = fdt_parent_offset(fdt, phy);
1075 if (mdio < 0) {
1076 pr_err("mdio dt not found\n");
1077 return -ENODEV;
1078 }
1079 priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
1080 }
1081
1082 if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
1083 priv->phy_if = PHY_INTERFACE_MODE_SGMII;
1084 pdata->phy_interface = priv->phy_if;
1085 priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
1086 priv->has_mdio = true;
1087 } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
1088 priv->phy_if = PHY_INTERFACE_MODE_RGMII;
1089 pdata->phy_interface = priv->phy_if;
1090 priv->has_mdio = true;
1091 }
1092
1093 return 0;
1094 }
1095
ks2_sl_eth_ofdata_to_platdata(struct udevice * dev)1096 static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
1097 {
1098 struct ks2_eth_priv *priv = dev_get_priv(dev);
1099 struct eth_pdata *pdata = dev_get_platdata(dev);
1100 const void *fdt = gd->fdt_blob;
1101 int slave = dev_of_offset(dev);
1102 int interfaces;
1103 int gbe;
1104 int netcp_devices;
1105 int netcp;
1106
1107 interfaces = fdt_parent_offset(fdt, slave);
1108 gbe = fdt_parent_offset(fdt, interfaces);
1109 netcp_devices = fdt_parent_offset(fdt, gbe);
1110 netcp = fdt_parent_offset(fdt, netcp_devices);
1111
1112 ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
1113
1114 pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
1115
1116 return 0;
1117 }
1118
ks2_eth_ofdata_to_platdata(struct udevice * dev)1119 static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
1120 {
1121 struct ks2_eth_priv *priv = dev_get_priv(dev);
1122 struct eth_pdata *pdata = dev_get_platdata(dev);
1123 const void *fdt = gd->fdt_blob;
1124 int gbe_0 = -ENODEV;
1125 int netcp_devices;
1126 int gbe;
1127
1128 netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
1129 "netcp-devices");
1130 gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
1131
1132 ks2_eth_bind_slaves(dev, gbe, &gbe_0);
1133
1134 ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
1135
1136 pdata->iobase = devfdt_get_addr(dev);
1137
1138 return 0;
1139 }
1140
1141 static const struct udevice_id ks2_eth_ids[] = {
1142 { .compatible = "ti,netcp-1.0" },
1143 { }
1144 };
1145
1146 U_BOOT_DRIVER(eth_ks2_slave) = {
1147 .name = "eth_ks2_sl",
1148 .id = UCLASS_ETH,
1149 .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
1150 .probe = ks2_eth_probe,
1151 .remove = ks2_eth_remove,
1152 .ops = &ks2_eth_ops,
1153 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
1154 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1155 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1156 };
1157
1158 U_BOOT_DRIVER(eth_ks2) = {
1159 .name = "eth_ks2",
1160 .id = UCLASS_ETH,
1161 .of_match = ks2_eth_ids,
1162 .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
1163 .probe = ks2_eth_probe,
1164 .remove = ks2_eth_remove,
1165 .ops = &ks2_eth_ops,
1166 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
1167 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1168 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1169 };
1170 #endif
1171