1 /*
2  * Copyright (C) 2015 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_
18 #define ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_
19 
20 #include "code_generator.h"
21 #include "instruction_simplifier_shared.h"
22 #include "locations.h"
23 #include "nodes.h"
24 #include "utils/arm64/assembler_arm64.h"
25 
26 // TODO(VIXL): Make VIXL compile with -Wshadow.
27 #pragma GCC diagnostic push
28 #pragma GCC diagnostic ignored "-Wshadow"
29 #include "aarch64/disasm-aarch64.h"
30 #include "aarch64/macro-assembler-aarch64.h"
31 #include "aarch64/simulator-aarch64.h"
32 #pragma GCC diagnostic pop
33 
34 namespace art {
35 
36 using helpers::CanFitInShifterOperand;
37 using helpers::HasShifterOperand;
38 
39 namespace arm64 {
40 namespace helpers {
41 
42 // Convenience helpers to ease conversion to and from VIXL operands.
43 static_assert((SP == 31) && (WSP == 31) && (XZR == 32) && (WZR == 32),
44               "Unexpected values for register codes.");
45 
VIXLRegCodeFromART(int code)46 inline int VIXLRegCodeFromART(int code) {
47   if (code == SP) {
48     return vixl::aarch64::kSPRegInternalCode;
49   }
50   if (code == XZR) {
51     return vixl::aarch64::kZeroRegCode;
52   }
53   return code;
54 }
55 
ARTRegCodeFromVIXL(int code)56 inline int ARTRegCodeFromVIXL(int code) {
57   if (code == vixl::aarch64::kSPRegInternalCode) {
58     return SP;
59   }
60   if (code == vixl::aarch64::kZeroRegCode) {
61     return XZR;
62   }
63   return code;
64 }
65 
XRegisterFrom(Location location)66 inline vixl::aarch64::Register XRegisterFrom(Location location) {
67   DCHECK(location.IsRegister()) << location;
68   return vixl::aarch64::Register::GetXRegFromCode(VIXLRegCodeFromART(location.reg()));
69 }
70 
WRegisterFrom(Location location)71 inline vixl::aarch64::Register WRegisterFrom(Location location) {
72   DCHECK(location.IsRegister()) << location;
73   return vixl::aarch64::Register::GetWRegFromCode(VIXLRegCodeFromART(location.reg()));
74 }
75 
RegisterFrom(Location location,DataType::Type type)76 inline vixl::aarch64::Register RegisterFrom(Location location, DataType::Type type) {
77   DCHECK(type != DataType::Type::kVoid && !DataType::IsFloatingPointType(type)) << type;
78   return type == DataType::Type::kInt64 ? XRegisterFrom(location) : WRegisterFrom(location);
79 }
80 
OutputRegister(HInstruction * instr)81 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) {
82   return RegisterFrom(instr->GetLocations()->Out(), instr->GetType());
83 }
84 
InputRegisterAt(HInstruction * instr,int input_index)85 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) {
86   return RegisterFrom(instr->GetLocations()->InAt(input_index),
87                       instr->InputAt(input_index)->GetType());
88 }
89 
DRegisterFrom(Location location)90 inline vixl::aarch64::VRegister DRegisterFrom(Location location) {
91   DCHECK(location.IsFpuRegister()) << location;
92   return vixl::aarch64::VRegister::GetDRegFromCode(location.reg());
93 }
94 
QRegisterFrom(Location location)95 inline vixl::aarch64::VRegister QRegisterFrom(Location location) {
96   DCHECK(location.IsFpuRegister()) << location;
97   return vixl::aarch64::VRegister::GetQRegFromCode(location.reg());
98 }
99 
VRegisterFrom(Location location)100 inline vixl::aarch64::VRegister VRegisterFrom(Location location) {
101   DCHECK(location.IsFpuRegister()) << location;
102   return vixl::aarch64::VRegister::GetVRegFromCode(location.reg());
103 }
104 
SRegisterFrom(Location location)105 inline vixl::aarch64::VRegister SRegisterFrom(Location location) {
106   DCHECK(location.IsFpuRegister()) << location;
107   return vixl::aarch64::VRegister::GetSRegFromCode(location.reg());
108 }
109 
HRegisterFrom(Location location)110 inline vixl::aarch64::VRegister HRegisterFrom(Location location) {
111   DCHECK(location.IsFpuRegister()) << location;
112   return vixl::aarch64::VRegister::GetHRegFromCode(location.reg());
113 }
114 
FPRegisterFrom(Location location,DataType::Type type)115 inline vixl::aarch64::VRegister FPRegisterFrom(Location location, DataType::Type type) {
116   DCHECK(DataType::IsFloatingPointType(type)) << type;
117   return type == DataType::Type::kFloat64 ? DRegisterFrom(location) : SRegisterFrom(location);
118 }
119 
OutputFPRegister(HInstruction * instr)120 inline vixl::aarch64::VRegister OutputFPRegister(HInstruction* instr) {
121   return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType());
122 }
123 
InputFPRegisterAt(HInstruction * instr,int input_index)124 inline vixl::aarch64::VRegister InputFPRegisterAt(HInstruction* instr, int input_index) {
125   return FPRegisterFrom(instr->GetLocations()->InAt(input_index),
126                         instr->InputAt(input_index)->GetType());
127 }
128 
CPURegisterFrom(Location location,DataType::Type type)129 inline vixl::aarch64::CPURegister CPURegisterFrom(Location location, DataType::Type type) {
130   return DataType::IsFloatingPointType(type)
131       ? vixl::aarch64::CPURegister(FPRegisterFrom(location, type))
132       : vixl::aarch64::CPURegister(RegisterFrom(location, type));
133 }
134 
OutputCPURegister(HInstruction * instr)135 inline vixl::aarch64::CPURegister OutputCPURegister(HInstruction* instr) {
136   return DataType::IsFloatingPointType(instr->GetType())
137       ? static_cast<vixl::aarch64::CPURegister>(OutputFPRegister(instr))
138       : static_cast<vixl::aarch64::CPURegister>(OutputRegister(instr));
139 }
140 
InputCPURegisterAt(HInstruction * instr,int index)141 inline vixl::aarch64::CPURegister InputCPURegisterAt(HInstruction* instr, int index) {
142   return DataType::IsFloatingPointType(instr->InputAt(index)->GetType())
143       ? static_cast<vixl::aarch64::CPURegister>(InputFPRegisterAt(instr, index))
144       : static_cast<vixl::aarch64::CPURegister>(InputRegisterAt(instr, index));
145 }
146 
InputCPURegisterOrZeroRegAt(HInstruction * instr,int index)147 inline vixl::aarch64::CPURegister InputCPURegisterOrZeroRegAt(HInstruction* instr,
148                                                                      int index) {
149   HInstruction* input = instr->InputAt(index);
150   DataType::Type input_type = input->GetType();
151   if (input->IsConstant() && input->AsConstant()->IsZeroBitPattern()) {
152     return (DataType::Size(input_type) >= vixl::aarch64::kXRegSizeInBytes)
153         ? vixl::aarch64::Register(vixl::aarch64::xzr)
154         : vixl::aarch64::Register(vixl::aarch64::wzr);
155   }
156   return InputCPURegisterAt(instr, index);
157 }
158 
Int64FromLocation(Location location)159 inline int64_t Int64FromLocation(Location location) {
160   return Int64FromConstant(location.GetConstant());
161 }
162 
OperandFrom(Location location,DataType::Type type)163 inline vixl::aarch64::Operand OperandFrom(Location location, DataType::Type type) {
164   if (location.IsRegister()) {
165     return vixl::aarch64::Operand(RegisterFrom(location, type));
166   } else {
167     return vixl::aarch64::Operand(Int64FromLocation(location));
168   }
169 }
170 
InputOperandAt(HInstruction * instr,int input_index)171 inline vixl::aarch64::Operand InputOperandAt(HInstruction* instr, int input_index) {
172   return OperandFrom(instr->GetLocations()->InAt(input_index),
173                      instr->InputAt(input_index)->GetType());
174 }
175 
StackOperandFrom(Location location)176 inline vixl::aarch64::MemOperand StackOperandFrom(Location location) {
177   return vixl::aarch64::MemOperand(vixl::aarch64::sp, location.GetStackIndex());
178 }
179 
180 inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base,
181                                                     size_t offset = 0) {
182   // A heap reference must be 32bit, so fit in a W register.
183   DCHECK(base.IsW());
184   return vixl::aarch64::MemOperand(base.X(), offset);
185 }
186 
187 inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base,
188                                                     const vixl::aarch64::Register& regoffset,
189                                                     vixl::aarch64::Shift shift = vixl::aarch64::LSL,
190                                                     unsigned shift_amount = 0) {
191   // A heap reference must be 32bit, so fit in a W register.
192   DCHECK(base.IsW());
193   return vixl::aarch64::MemOperand(base.X(), regoffset, shift, shift_amount);
194 }
195 
HeapOperand(const vixl::aarch64::Register & base,Offset offset)196 inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base,
197                                                     Offset offset) {
198   return HeapOperand(base, offset.SizeValue());
199 }
200 
HeapOperandFrom(Location location,Offset offset)201 inline vixl::aarch64::MemOperand HeapOperandFrom(Location location, Offset offset) {
202   return HeapOperand(RegisterFrom(location, DataType::Type::kReference), offset);
203 }
204 
LocationFrom(const vixl::aarch64::Register & reg)205 inline Location LocationFrom(const vixl::aarch64::Register& reg) {
206   return Location::RegisterLocation(ARTRegCodeFromVIXL(reg.GetCode()));
207 }
208 
LocationFrom(const vixl::aarch64::VRegister & fpreg)209 inline Location LocationFrom(const vixl::aarch64::VRegister& fpreg) {
210   return Location::FpuRegisterLocation(fpreg.GetCode());
211 }
212 
OperandFromMemOperand(const vixl::aarch64::MemOperand & mem_op)213 inline vixl::aarch64::Operand OperandFromMemOperand(
214     const vixl::aarch64::MemOperand& mem_op) {
215   if (mem_op.IsImmediateOffset()) {
216     return vixl::aarch64::Operand(mem_op.GetOffset());
217   } else {
218     DCHECK(mem_op.IsRegisterOffset());
219     if (mem_op.GetExtend() != vixl::aarch64::NO_EXTEND) {
220       return vixl::aarch64::Operand(mem_op.GetRegisterOffset(),
221                                     mem_op.GetExtend(),
222                                     mem_op.GetShiftAmount());
223     } else if (mem_op.GetShift() != vixl::aarch64::NO_SHIFT) {
224       return vixl::aarch64::Operand(mem_op.GetRegisterOffset(),
225                                     mem_op.GetShift(),
226                                     mem_op.GetShiftAmount());
227     } else {
228       LOG(FATAL) << "Should not reach here";
229       UNREACHABLE();
230     }
231   }
232 }
233 
AddSubCanEncodeAsImmediate(int64_t value)234 inline bool AddSubCanEncodeAsImmediate(int64_t value) {
235   // If `value` does not fit but `-value` does, VIXL will automatically use
236   // the 'opposite' instruction.
237   return vixl::aarch64::Assembler::IsImmAddSub(value)
238       || vixl::aarch64::Assembler::IsImmAddSub(-value);
239 }
240 
Arm64CanEncodeConstantAsImmediate(HConstant * constant,HInstruction * instr)241 inline bool Arm64CanEncodeConstantAsImmediate(HConstant* constant, HInstruction* instr) {
242   int64_t value = CodeGenerator::GetInt64ValueOf(constant);
243 
244   // TODO: Improve this when IsSIMDConstantEncodable method is implemented in VIXL.
245   if (instr->IsVecReplicateScalar()) {
246     if (constant->IsLongConstant()) {
247       return false;
248     } else if (constant->IsFloatConstant()) {
249       return vixl::aarch64::Assembler::IsImmFP32(constant->AsFloatConstant()->GetValue());
250     } else if (constant->IsDoubleConstant()) {
251       return vixl::aarch64::Assembler::IsImmFP64(constant->AsDoubleConstant()->GetValue());
252     }
253     return IsUint<8>(value);
254   }
255 
256   // Code generation for Min/Max:
257   //    Cmp left_op, right_op
258   //    Csel dst, left_op, right_op, cond
259   if (instr->IsMin() || instr->IsMax()) {
260     if (constant->GetUses().HasExactlyOneElement()) {
261       // If value can be encoded as immediate for the Cmp, then let VIXL handle
262       // the constant generation for the Csel.
263       return AddSubCanEncodeAsImmediate(value);
264     }
265     // These values are encodable as immediates for Cmp and VIXL will use csinc and csinv
266     // with the zr register as right_op, hence no constant generation is required.
267     return constant->IsZeroBitPattern() || constant->IsOne() || constant->IsMinusOne();
268   }
269 
270   // For single uses we let VIXL handle the constant generation since it will
271   // use registers that are not managed by the register allocator (wip0, wip1).
272   if (constant->GetUses().HasExactlyOneElement()) {
273     return true;
274   }
275 
276   // Our code generator ensures shift distances are within an encodable range.
277   if (instr->IsRor()) {
278     return true;
279   }
280 
281   if (instr->IsAnd() || instr->IsOr() || instr->IsXor()) {
282     // Uses logical operations.
283     return vixl::aarch64::Assembler::IsImmLogical(value, vixl::aarch64::kXRegSize);
284   } else if (instr->IsNeg()) {
285     // Uses mov -immediate.
286     return vixl::aarch64::Assembler::IsImmMovn(value, vixl::aarch64::kXRegSize);
287   } else {
288     DCHECK(instr->IsAdd() ||
289            instr->IsIntermediateAddress() ||
290            instr->IsBoundsCheck() ||
291            instr->IsCompare() ||
292            instr->IsCondition() ||
293            instr->IsSub())
294         << instr->DebugName();
295     // Uses aliases of ADD/SUB instructions.
296     return AddSubCanEncodeAsImmediate(value);
297   }
298 }
299 
ARM64EncodableConstantOrRegister(HInstruction * constant,HInstruction * instr)300 inline Location ARM64EncodableConstantOrRegister(HInstruction* constant,
301                                                         HInstruction* instr) {
302   if (constant->IsConstant()
303       && Arm64CanEncodeConstantAsImmediate(constant->AsConstant(), instr)) {
304     return Location::ConstantLocation(constant->AsConstant());
305   }
306 
307   return Location::RequiresRegister();
308 }
309 
310 // Check if registers in art register set have the same register code in vixl. If the register
311 // codes are same, we can initialize vixl register list simply by the register masks. Currently,
312 // only SP/WSP and ZXR/WZR codes are different between art and vixl.
313 // Note: This function is only used for debug checks.
ArtVixlRegCodeCoherentForRegSet(uint32_t art_core_registers,size_t num_core,uint32_t art_fpu_registers,size_t num_fpu)314 inline bool ArtVixlRegCodeCoherentForRegSet(uint32_t art_core_registers,
315                                             size_t num_core,
316                                             uint32_t art_fpu_registers,
317                                             size_t num_fpu) {
318   // The register masks won't work if the number of register is larger than 32.
319   DCHECK_GE(sizeof(art_core_registers) * 8, num_core);
320   DCHECK_GE(sizeof(art_fpu_registers) * 8, num_fpu);
321   for (size_t art_reg_code = 0;  art_reg_code < num_core; ++art_reg_code) {
322     if (RegisterSet::Contains(art_core_registers, art_reg_code)) {
323       if (art_reg_code != static_cast<size_t>(VIXLRegCodeFromART(art_reg_code))) {
324         return false;
325       }
326     }
327   }
328   // There is no register code translation for float registers.
329   return true;
330 }
331 
ShiftFromOpKind(HDataProcWithShifterOp::OpKind op_kind)332 inline vixl::aarch64::Shift ShiftFromOpKind(HDataProcWithShifterOp::OpKind op_kind) {
333   switch (op_kind) {
334     case HDataProcWithShifterOp::kASR: return vixl::aarch64::ASR;
335     case HDataProcWithShifterOp::kLSL: return vixl::aarch64::LSL;
336     case HDataProcWithShifterOp::kLSR: return vixl::aarch64::LSR;
337     default:
338       LOG(FATAL) << "Unexpected op kind " << op_kind;
339       UNREACHABLE();
340       return vixl::aarch64::NO_SHIFT;
341   }
342 }
343 
ExtendFromOpKind(HDataProcWithShifterOp::OpKind op_kind)344 inline vixl::aarch64::Extend ExtendFromOpKind(HDataProcWithShifterOp::OpKind op_kind) {
345   switch (op_kind) {
346     case HDataProcWithShifterOp::kUXTB: return vixl::aarch64::UXTB;
347     case HDataProcWithShifterOp::kUXTH: return vixl::aarch64::UXTH;
348     case HDataProcWithShifterOp::kUXTW: return vixl::aarch64::UXTW;
349     case HDataProcWithShifterOp::kSXTB: return vixl::aarch64::SXTB;
350     case HDataProcWithShifterOp::kSXTH: return vixl::aarch64::SXTH;
351     case HDataProcWithShifterOp::kSXTW: return vixl::aarch64::SXTW;
352     default:
353       LOG(FATAL) << "Unexpected op kind " << op_kind;
354       UNREACHABLE();
355       return vixl::aarch64::NO_EXTEND;
356   }
357 }
358 
ShifterOperandSupportsExtension(HInstruction * instruction)359 inline bool ShifterOperandSupportsExtension(HInstruction* instruction) {
360   DCHECK(HasShifterOperand(instruction, InstructionSet::kArm64));
361   // Although the `neg` instruction is an alias of the `sub` instruction, `HNeg`
362   // does *not* support extension. This is because the `extended register` form
363   // of the `sub` instruction interprets the left register with code 31 as the
364   // stack pointer and not the zero register. (So does the `immediate` form.) In
365   // the other form `shifted register, the register with code 31 is interpreted
366   // as the zero register.
367   return instruction->IsAdd() || instruction->IsSub();
368 }
369 
IsConstantZeroBitPattern(const HInstruction * instruction)370 inline bool IsConstantZeroBitPattern(const HInstruction* instruction) {
371   return instruction->IsConstant() && instruction->AsConstant()->IsZeroBitPattern();
372 }
373 
374 }  // namespace helpers
375 }  // namespace arm64
376 }  // namespace art
377 
378 #endif  // ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_
379