1 /*
2  * Copyright (C) 2011 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef ART_LIBDEXFILE_DEX_DEX_INSTRUCTION_INL_H_
18 #define ART_LIBDEXFILE_DEX_DEX_INSTRUCTION_INL_H_
19 
20 #include "dex_instruction.h"
21 
22 namespace art {
23 
SizeInCodeUnits(Format format)24 inline constexpr size_t Instruction::SizeInCodeUnits(Format format) {
25   switch (format) {
26     case k10x:
27     case k12x:
28     case k11n:
29     case k11x:
30     case k10t: return 1;
31     case k20t:
32     case k22x:
33     case k21t:
34     case k21s:
35     case k21h:
36     case k21c:
37     case k23x:
38     case k22b:
39     case k22t:
40     case k22s:
41     case k22c: return 2;
42     case k32x:
43     case k30t:
44     case k31t:
45     case k31i:
46     case k31c:
47     case k35c:
48     case k3rc: return 3;
49     case k45cc:
50     case k4rcc: return 4;
51     case k51l: return 5;
52     case kInvalidFormat: return 0;
53   }
54 }
55 
56 //------------------------------------------------------------------------------
57 // VRegA
58 //------------------------------------------------------------------------------
HasVRegA()59 inline bool Instruction::HasVRegA() const {
60   switch (FormatOf(Opcode())) {
61     case k10t: return true;
62     case k10x: return true;
63     case k11n: return true;
64     case k11x: return true;
65     case k12x: return true;
66     case k20t: return true;
67     case k21c: return true;
68     case k21h: return true;
69     case k21s: return true;
70     case k21t: return true;
71     case k22b: return true;
72     case k22c: return true;
73     case k22s: return true;
74     case k22t: return true;
75     case k22x: return true;
76     case k23x: return true;
77     case k30t: return true;
78     case k31c: return true;
79     case k31i: return true;
80     case k31t: return true;
81     case k32x: return true;
82     case k35c: return true;
83     case k3rc: return true;
84     case k45cc: return true;
85     case k4rcc: return true;
86     case k51l: return true;
87     default: return false;
88   }
89 }
90 
VRegA()91 inline int32_t Instruction::VRegA() const {
92   return VRegA(FormatOf(Opcode()), Fetch16(0));
93 }
94 
VRegA(Format format,uint16_t inst_data)95 inline int32_t Instruction::VRegA(Format format, uint16_t inst_data) const {
96   DCHECK_EQ(format, FormatOf(Opcode()));
97   switch (format) {
98     case k10t: return VRegA_10t(inst_data);
99     case k10x: return VRegA_10x(inst_data);
100     case k11n: return VRegA_11n(inst_data);
101     case k11x: return VRegA_11x(inst_data);
102     case k12x: return VRegA_12x(inst_data);
103     case k20t: return VRegA_20t();
104     case k21c: return VRegA_21c(inst_data);
105     case k21h: return VRegA_21h(inst_data);
106     case k21s: return VRegA_21s(inst_data);
107     case k21t: return VRegA_21t(inst_data);
108     case k22b: return VRegA_22b(inst_data);
109     case k22c: return VRegA_22c(inst_data);
110     case k22s: return VRegA_22s(inst_data);
111     case k22t: return VRegA_22t(inst_data);
112     case k22x: return VRegA_22x(inst_data);
113     case k23x: return VRegA_23x(inst_data);
114     case k30t: return VRegA_30t();
115     case k31c: return VRegA_31c(inst_data);
116     case k31i: return VRegA_31i(inst_data);
117     case k31t: return VRegA_31t(inst_data);
118     case k32x: return VRegA_32x();
119     case k35c: return VRegA_35c(inst_data);
120     case k3rc: return VRegA_3rc(inst_data);
121     case k45cc: return VRegA_45cc(inst_data);
122     case k4rcc: return VRegA_4rcc(inst_data);
123     case k51l: return VRegA_51l(inst_data);
124     default:
125       LOG(FATAL) << "Tried to access vA of instruction " << Name() << " which has no A operand.";
126       exit(EXIT_FAILURE);
127   }
128 }
129 
VRegA_10t(uint16_t inst_data)130 inline int8_t Instruction::VRegA_10t(uint16_t inst_data) const {
131   DCHECK_EQ(FormatOf(Opcode()), k10t);
132   return static_cast<int8_t>(InstAA(inst_data));
133 }
134 
VRegA_10x(uint16_t inst_data)135 inline uint8_t Instruction::VRegA_10x(uint16_t inst_data) const {
136   DCHECK_EQ(FormatOf(Opcode()), k10x);
137   return InstAA(inst_data);
138 }
139 
VRegA_11n(uint16_t inst_data)140 inline uint4_t Instruction::VRegA_11n(uint16_t inst_data) const {
141   DCHECK_EQ(FormatOf(Opcode()), k11n);
142   return InstA(inst_data);
143 }
144 
VRegA_11x(uint16_t inst_data)145 inline uint8_t Instruction::VRegA_11x(uint16_t inst_data) const {
146   DCHECK_EQ(FormatOf(Opcode()), k11x);
147   return InstAA(inst_data);
148 }
149 
VRegA_12x(uint16_t inst_data)150 inline uint4_t Instruction::VRegA_12x(uint16_t inst_data) const {
151   DCHECK_EQ(FormatOf(Opcode()), k12x);
152   return InstA(inst_data);
153 }
154 
VRegA_20t()155 inline int16_t Instruction::VRegA_20t() const {
156   DCHECK_EQ(FormatOf(Opcode()), k20t);
157   return static_cast<int16_t>(Fetch16(1));
158 }
159 
VRegA_21c(uint16_t inst_data)160 inline uint8_t Instruction::VRegA_21c(uint16_t inst_data) const {
161   DCHECK_EQ(FormatOf(Opcode()), k21c);
162   return InstAA(inst_data);
163 }
164 
VRegA_21h(uint16_t inst_data)165 inline uint8_t Instruction::VRegA_21h(uint16_t inst_data) const {
166   DCHECK_EQ(FormatOf(Opcode()), k21h);
167   return InstAA(inst_data);
168 }
169 
VRegA_21s(uint16_t inst_data)170 inline uint8_t Instruction::VRegA_21s(uint16_t inst_data) const {
171   DCHECK_EQ(FormatOf(Opcode()), k21s);
172   return InstAA(inst_data);
173 }
174 
VRegA_21t(uint16_t inst_data)175 inline uint8_t Instruction::VRegA_21t(uint16_t inst_data) const {
176   DCHECK_EQ(FormatOf(Opcode()), k21t);
177   return InstAA(inst_data);
178 }
179 
VRegA_22b(uint16_t inst_data)180 inline uint8_t Instruction::VRegA_22b(uint16_t inst_data) const {
181   DCHECK_EQ(FormatOf(Opcode()), k22b);
182   return InstAA(inst_data);
183 }
184 
VRegA_22c(uint16_t inst_data)185 inline uint4_t Instruction::VRegA_22c(uint16_t inst_data) const {
186   DCHECK_EQ(FormatOf(Opcode()), k22c);
187   return InstA(inst_data);
188 }
189 
VRegA_22s(uint16_t inst_data)190 inline uint4_t Instruction::VRegA_22s(uint16_t inst_data) const {
191   DCHECK_EQ(FormatOf(Opcode()), k22s);
192   return InstA(inst_data);
193 }
194 
VRegA_22t(uint16_t inst_data)195 inline uint4_t Instruction::VRegA_22t(uint16_t inst_data) const {
196   DCHECK_EQ(FormatOf(Opcode()), k22t);
197   return InstA(inst_data);
198 }
199 
VRegA_22x(uint16_t inst_data)200 inline uint8_t Instruction::VRegA_22x(uint16_t inst_data) const {
201   DCHECK_EQ(FormatOf(Opcode()), k22x);
202   return InstAA(inst_data);
203 }
204 
VRegA_23x(uint16_t inst_data)205 inline uint8_t Instruction::VRegA_23x(uint16_t inst_data) const {
206   DCHECK_EQ(FormatOf(Opcode()), k23x);
207   return InstAA(inst_data);
208 }
209 
VRegA_30t()210 inline int32_t Instruction::VRegA_30t() const {
211   DCHECK_EQ(FormatOf(Opcode()), k30t);
212   return static_cast<int32_t>(Fetch32(1));
213 }
214 
VRegA_31c(uint16_t inst_data)215 inline uint8_t Instruction::VRegA_31c(uint16_t inst_data) const {
216   DCHECK_EQ(FormatOf(Opcode()), k31c);
217   return InstAA(inst_data);
218 }
219 
VRegA_31i(uint16_t inst_data)220 inline uint8_t Instruction::VRegA_31i(uint16_t inst_data) const {
221   DCHECK_EQ(FormatOf(Opcode()), k31i);
222   return InstAA(inst_data);
223 }
224 
VRegA_31t(uint16_t inst_data)225 inline uint8_t Instruction::VRegA_31t(uint16_t inst_data) const {
226   DCHECK_EQ(FormatOf(Opcode()), k31t);
227   return InstAA(inst_data);
228 }
229 
VRegA_32x()230 inline uint16_t Instruction::VRegA_32x() const {
231   DCHECK_EQ(FormatOf(Opcode()), k32x);
232   return Fetch16(1);
233 }
234 
VRegA_35c(uint16_t inst_data)235 inline uint4_t Instruction::VRegA_35c(uint16_t inst_data) const {
236   DCHECK_EQ(FormatOf(Opcode()), k35c);
237   return InstB(inst_data);  // This is labeled A in the spec.
238 }
239 
VRegA_3rc(uint16_t inst_data)240 inline uint8_t Instruction::VRegA_3rc(uint16_t inst_data) const {
241   DCHECK_EQ(FormatOf(Opcode()), k3rc);
242   return InstAA(inst_data);
243 }
244 
VRegA_51l(uint16_t inst_data)245 inline uint8_t Instruction::VRegA_51l(uint16_t inst_data) const {
246   DCHECK_EQ(FormatOf(Opcode()), k51l);
247   return InstAA(inst_data);
248 }
249 
VRegA_45cc(uint16_t inst_data)250 inline uint4_t Instruction::VRegA_45cc(uint16_t inst_data) const {
251   DCHECK_EQ(FormatOf(Opcode()), k45cc);
252   return InstB(inst_data);  // This is labeled A in the spec.
253 }
254 
VRegA_4rcc(uint16_t inst_data)255 inline uint8_t Instruction::VRegA_4rcc(uint16_t inst_data) const {
256   DCHECK_EQ(FormatOf(Opcode()), k4rcc);
257   return InstAA(inst_data);
258 }
259 
260 //------------------------------------------------------------------------------
261 // VRegB
262 //------------------------------------------------------------------------------
HasVRegB()263 inline bool Instruction::HasVRegB() const {
264   switch (FormatOf(Opcode())) {
265     case k11n: return true;
266     case k12x: return true;
267     case k21c: return true;
268     case k21h: return true;
269     case k21s: return true;
270     case k21t: return true;
271     case k22b: return true;
272     case k22c: return true;
273     case k22s: return true;
274     case k22t: return true;
275     case k22x: return true;
276     case k23x: return true;
277     case k31c: return true;
278     case k31i: return true;
279     case k31t: return true;
280     case k32x: return true;
281     case k35c: return true;
282     case k3rc: return true;
283     case k45cc: return true;
284     case k4rcc: return true;
285     case k51l: return true;
286     default: return false;
287   }
288 }
289 
HasWideVRegB()290 inline bool Instruction::HasWideVRegB() const {
291   return FormatOf(Opcode()) == k51l;
292 }
293 
VRegB()294 inline int32_t Instruction::VRegB() const {
295   return VRegB(FormatOf(Opcode()), Fetch16(0));
296 }
297 
VRegB(Format format,uint16_t inst_data)298 inline int32_t Instruction::VRegB(Format format, uint16_t inst_data) const {
299   DCHECK_EQ(format, FormatOf(Opcode()));
300   switch (format) {
301     case k11n: return VRegB_11n(inst_data);
302     case k12x: return VRegB_12x(inst_data);
303     case k21c: return VRegB_21c();
304     case k21h: return VRegB_21h();
305     case k21s: return VRegB_21s();
306     case k21t: return VRegB_21t();
307     case k22b: return VRegB_22b();
308     case k22c: return VRegB_22c(inst_data);
309     case k22s: return VRegB_22s(inst_data);
310     case k22t: return VRegB_22t(inst_data);
311     case k22x: return VRegB_22x();
312     case k23x: return VRegB_23x();
313     case k31c: return VRegB_31c();
314     case k31i: return VRegB_31i();
315     case k31t: return VRegB_31t();
316     case k32x: return VRegB_32x();
317     case k35c: return VRegB_35c();
318     case k3rc: return VRegB_3rc();
319     case k45cc: return VRegB_45cc();
320     case k4rcc: return VRegB_4rcc();
321     case k51l: return VRegB_51l();
322     default:
323       LOG(FATAL) << "Tried to access vB of instruction " << Name() << " which has no B operand.";
324       exit(EXIT_FAILURE);
325   }
326 }
327 
WideVRegB()328 inline uint64_t Instruction::WideVRegB() const {
329   return VRegB_51l();
330 }
331 
VRegB_11n(uint16_t inst_data)332 inline int4_t Instruction::VRegB_11n(uint16_t inst_data) const {
333   DCHECK_EQ(FormatOf(Opcode()), k11n);
334   return static_cast<int4_t>((InstB(inst_data) << 28) >> 28);
335 }
336 
VRegB_12x(uint16_t inst_data)337 inline uint4_t Instruction::VRegB_12x(uint16_t inst_data) const {
338   DCHECK_EQ(FormatOf(Opcode()), k12x);
339   return InstB(inst_data);
340 }
341 
VRegB_21c()342 inline uint16_t Instruction::VRegB_21c() const {
343   DCHECK_EQ(FormatOf(Opcode()), k21c);
344   return Fetch16(1);
345 }
346 
VRegB_21h()347 inline uint16_t Instruction::VRegB_21h() const {
348   DCHECK_EQ(FormatOf(Opcode()), k21h);
349   return Fetch16(1);
350 }
351 
VRegB_21s()352 inline int16_t Instruction::VRegB_21s() const {
353   DCHECK_EQ(FormatOf(Opcode()), k21s);
354   return static_cast<int16_t>(Fetch16(1));
355 }
356 
VRegB_21t()357 inline int16_t Instruction::VRegB_21t() const {
358   DCHECK_EQ(FormatOf(Opcode()), k21t);
359   return static_cast<int16_t>(Fetch16(1));
360 }
361 
VRegB_22b()362 inline uint8_t Instruction::VRegB_22b() const {
363   DCHECK_EQ(FormatOf(Opcode()), k22b);
364   return static_cast<uint8_t>(Fetch16(1) & 0xff);
365 }
366 
VRegB_22c(uint16_t inst_data)367 inline uint4_t Instruction::VRegB_22c(uint16_t inst_data) const {
368   DCHECK_EQ(FormatOf(Opcode()), k22c);
369   return InstB(inst_data);
370 }
371 
VRegB_22s(uint16_t inst_data)372 inline uint4_t Instruction::VRegB_22s(uint16_t inst_data) const {
373   DCHECK_EQ(FormatOf(Opcode()), k22s);
374   return InstB(inst_data);
375 }
376 
VRegB_22t(uint16_t inst_data)377 inline uint4_t Instruction::VRegB_22t(uint16_t inst_data) const {
378   DCHECK_EQ(FormatOf(Opcode()), k22t);
379   return InstB(inst_data);
380 }
381 
VRegB_22x()382 inline uint16_t Instruction::VRegB_22x() const {
383   DCHECK_EQ(FormatOf(Opcode()), k22x);
384   return Fetch16(1);
385 }
386 
VRegB_23x()387 inline uint8_t Instruction::VRegB_23x() const {
388   DCHECK_EQ(FormatOf(Opcode()), k23x);
389   return static_cast<uint8_t>(Fetch16(1) & 0xff);
390 }
391 
VRegB_31c()392 inline uint32_t Instruction::VRegB_31c() const {
393   DCHECK_EQ(FormatOf(Opcode()), k31c);
394   return Fetch32(1);
395 }
396 
VRegB_31i()397 inline int32_t Instruction::VRegB_31i() const {
398   DCHECK_EQ(FormatOf(Opcode()), k31i);
399   return static_cast<int32_t>(Fetch32(1));
400 }
401 
VRegB_31t()402 inline int32_t Instruction::VRegB_31t() const {
403   DCHECK_EQ(FormatOf(Opcode()), k31t);
404   return static_cast<int32_t>(Fetch32(1));
405 }
406 
VRegB_32x()407 inline uint16_t Instruction::VRegB_32x() const {
408   DCHECK_EQ(FormatOf(Opcode()), k32x);
409   return Fetch16(2);
410 }
411 
VRegB_35c()412 inline uint16_t Instruction::VRegB_35c() const {
413   DCHECK_EQ(FormatOf(Opcode()), k35c);
414   return Fetch16(1);
415 }
416 
VRegB_3rc()417 inline uint16_t Instruction::VRegB_3rc() const {
418   DCHECK_EQ(FormatOf(Opcode()), k3rc);
419   return Fetch16(1);
420 }
421 
VRegB_45cc()422 inline uint16_t Instruction::VRegB_45cc() const {
423   DCHECK_EQ(FormatOf(Opcode()), k45cc);
424   return Fetch16(1);
425 }
426 
VRegB_4rcc()427 inline uint16_t Instruction::VRegB_4rcc() const {
428   DCHECK_EQ(FormatOf(Opcode()), k4rcc);
429   return Fetch16(1);
430 }
431 
VRegB_51l()432 inline uint64_t Instruction::VRegB_51l() const {
433   DCHECK_EQ(FormatOf(Opcode()), k51l);
434   uint64_t vB_wide = Fetch32(1) | ((uint64_t) Fetch32(3) << 32);
435   return vB_wide;
436 }
437 
438 //------------------------------------------------------------------------------
439 // VRegC
440 //------------------------------------------------------------------------------
HasVRegC()441 inline bool Instruction::HasVRegC() const {
442   switch (FormatOf(Opcode())) {
443     case k22b: return true;
444     case k22c: return true;
445     case k22s: return true;
446     case k22t: return true;
447     case k23x: return true;
448     case k35c: return true;
449     case k3rc: return true;
450     case k45cc: return true;
451     case k4rcc: return true;
452     default: return false;
453   }
454 }
455 
VRegC()456 inline int32_t Instruction::VRegC() const {
457   return VRegC(FormatOf(Opcode()));
458 }
459 
VRegC(Format format)460 inline int32_t Instruction::VRegC(Format format) const {
461   DCHECK_EQ(format, FormatOf(Opcode()));
462   switch (format) {
463     case k22b: return VRegC_22b();
464     case k22c: return VRegC_22c();
465     case k22s: return VRegC_22s();
466     case k22t: return VRegC_22t();
467     case k23x: return VRegC_23x();
468     case k35c: return VRegC_35c();
469     case k3rc: return VRegC_3rc();
470     case k45cc: return VRegC_45cc();
471     case k4rcc: return VRegC_4rcc();
472     default:
473       LOG(FATAL) << "Tried to access vC of instruction " << Name() << " which has no C operand.";
474       exit(EXIT_FAILURE);
475   }
476 }
477 
VRegC_22b()478 inline int8_t Instruction::VRegC_22b() const {
479   DCHECK_EQ(FormatOf(Opcode()), k22b);
480   return static_cast<int8_t>(Fetch16(1) >> 8);
481 }
482 
VRegC_22c()483 inline uint16_t Instruction::VRegC_22c() const {
484   DCHECK_EQ(FormatOf(Opcode()), k22c);
485   return Fetch16(1);
486 }
487 
VRegC_22s()488 inline int16_t Instruction::VRegC_22s() const {
489   DCHECK_EQ(FormatOf(Opcode()), k22s);
490   return static_cast<int16_t>(Fetch16(1));
491 }
492 
VRegC_22t()493 inline int16_t Instruction::VRegC_22t() const {
494   DCHECK_EQ(FormatOf(Opcode()), k22t);
495   return static_cast<int16_t>(Fetch16(1));
496 }
497 
VRegC_23x()498 inline uint8_t Instruction::VRegC_23x() const {
499   DCHECK_EQ(FormatOf(Opcode()), k23x);
500   return static_cast<uint8_t>(Fetch16(1) >> 8);
501 }
502 
VRegC_35c()503 inline uint4_t Instruction::VRegC_35c() const {
504   DCHECK_EQ(FormatOf(Opcode()), k35c);
505   return static_cast<uint4_t>(Fetch16(2) & 0x0f);
506 }
507 
VRegC_3rc()508 inline uint16_t Instruction::VRegC_3rc() const {
509   DCHECK_EQ(FormatOf(Opcode()), k3rc);
510   return Fetch16(2);
511 }
512 
VRegC_45cc()513 inline uint4_t Instruction::VRegC_45cc() const {
514   DCHECK_EQ(FormatOf(Opcode()), k45cc);
515   return static_cast<uint4_t>(Fetch16(2) & 0x0f);
516 }
517 
VRegC_4rcc()518 inline uint16_t Instruction::VRegC_4rcc() const {
519   DCHECK_EQ(FormatOf(Opcode()), k4rcc);
520   return Fetch16(2);
521 }
522 
523 //------------------------------------------------------------------------------
524 // VRegH
525 //------------------------------------------------------------------------------
HasVRegH()526 inline bool Instruction::HasVRegH() const {
527   switch (FormatOf(Opcode())) {
528     case k45cc: return true;
529     case k4rcc: return true;
530     default : return false;
531   }
532 }
533 
VRegH()534 inline int32_t Instruction::VRegH() const {
535   switch (FormatOf(Opcode())) {
536     case k45cc: return VRegH_45cc();
537     case k4rcc: return VRegH_4rcc();
538     default :
539       LOG(FATAL) << "Tried to access vH of instruction " << Name() << " which has no H operand.";
540       exit(EXIT_FAILURE);
541   }
542 }
543 
VRegH_45cc()544 inline uint16_t Instruction::VRegH_45cc() const {
545   DCHECK_EQ(FormatOf(Opcode()), k45cc);
546   return Fetch16(3);
547 }
548 
VRegH_4rcc()549 inline uint16_t Instruction::VRegH_4rcc() const {
550   DCHECK_EQ(FormatOf(Opcode()), k4rcc);
551   return Fetch16(3);
552 }
553 
HasVarArgs()554 inline bool Instruction::HasVarArgs() const {
555   return (FormatOf(Opcode()) == k35c) || (FormatOf(Opcode()) == k45cc);
556 }
557 
GetVarArgs(uint32_t arg[kMaxVarArgRegs],uint16_t inst_data)558 inline uint32_t Instruction::GetVarArgs(uint32_t arg[kMaxVarArgRegs], uint16_t inst_data) const {
559   DCHECK(HasVarArgs());
560 
561   /*
562    * Note that the fields mentioned in the spec don't appear in
563    * their "usual" positions here compared to most formats. This
564    * was done so that the field names for the argument count and
565    * reference index match between this format and the corresponding
566    * range formats (3rc and friends).
567    *
568    * Bottom line: The argument count is always in vA, and the
569    * method constant (or equivalent) is always in vB.
570    */
571   uint16_t regList = Fetch16(2);
572   uint4_t count = InstB(inst_data);  // This is labeled A in the spec.
573   DCHECK_LE(count, 5U) << "Invalid arg count in 35c (" << count << ")";
574 
575   /*
576    * Copy the argument registers into the arg[] array, and
577    * also copy the first argument (if any) into vC. (The
578    * DecodedInstruction structure doesn't have separate
579    * fields for {vD, vE, vF, vG}, so there's no need to make
580    * copies of those.) Note that cases 5..2 fall through.
581    */
582   switch (count) {
583     case 5:
584       arg[4] = InstA(inst_data);
585       FALLTHROUGH_INTENDED;
586     case 4:
587       arg[3] = (regList >> 12) & 0x0f;
588       FALLTHROUGH_INTENDED;
589     case 3:
590       arg[2] = (regList >> 8) & 0x0f;
591       FALLTHROUGH_INTENDED;
592     case 2:
593       arg[1] = (regList >> 4) & 0x0f;
594       FALLTHROUGH_INTENDED;
595     case 1:
596       arg[0] = regList & 0x0f;
597       break;
598     default:  // case 0
599       break;  // Valid, but no need to do anything.
600   }
601   return count;
602 }
603 
604 }  // namespace art
605 
606 #endif  // ART_LIBDEXFILE_DEX_DEX_INSTRUCTION_INL_H_
607