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/frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/
Dconvolve_neon.s41 ADD r5, r3, #1 @ i = n + 1
45 SUB r5, r5, #1
50 CMP r5, #0
57 SUBS r5, r5, #4
63 VMOV.S32 r5, D20[0]
64 ADD r5, r5, r8
65 ADD r5, r11, r5, LSL #1
66 MOV r5, r5, LSR #16 @extract_h(s)
68 STRH r5, [r2], #2 @y[n]
73 ADD r5, r3, #1
[all …]
Dcor_h_vec_neon.s31 @r5 ---- cor_1[]
48 MOV r5, #0 @L_sum1 = 0
59 MLA r5, r12, r8, r5
65 MLA r5, r12, r14, r5
67 MOV r5, r5, LSL #2 @L_sum1 = (L_sum1 << 2)
69 ADD r9, r5, r14
70 MOV r5, r9, ASR #16
76 MUL r12, r5, r10
78 MOV r5, r12, ASR #15
86 ADD r5, r5, r10
[all …]
DNorm_Corr_neon.s31 @ r5 --- t_max
59 ADD r5, r0, r11, LSL #1 @get the &exc[k]
63 MOV r0, r5
165 VMOV.S32 r5, D22[0]
167 @r5 --- L_tmp, r6 --- L_tmp1
169 ADD r5, r10, r5, LSL #1 @L_tmp = (L_tmp << 1) + 1
172 CLZ r10, r5
173 CMP r5, #0
174 RSBLT r11, r5, #0
178 MOV r5, r5, LSL r10 @L_tmp = (L_tmp << exp)
[all …]
Dsyn_filt_neon.s39 MOV r5, r13 @ copy yy = y_buf address
46 VST1.S16 {D0, D1, D2, D3}, [r5]! @store 16 mem[] to *yy
48 LDRSH r5, [r0], #2 @ load a[0]
50 MOV r5, r5, ASR #1 @ a0 = a[0] >> 1
51 VMOV.S16 D8[0], r5
67 MUL r12, r6, r5 @ L_tmp = x[i] * a0
95 ADD r5, r13, #160 @ yy[64] address
96 VLD1.S16 {D0, D1, D2, D3}, [r5]!
DDeemph_32_neon.s40 LDR r5, =22282 @r5---mu
45 MOV r8, r5, ASR #1 @fac = mu >> 1
46 LDR r5, [r3]
49 MUL r9, r5, r8
DFilt_6k_7k_neon.s38 MOV r5, r2 @ copy mem[] address
84 MOV r12, r5
85 @STR r5, [sp, #-4] @ PUSH r5 to stack
86 @ not use registers: r4, r10, r12, r14, r5
88 MOV r5, #0 @ i = 0
93 VMOV.S16 D7[3], r5 @set fir_6k_7K = 0
204 ADD r5, r5, #8
205 CMP r5, #80
Dscale_sig_neon.s37 MOV r5, r0 @ copy x[] address
51 VLD1.S16 {Q0, Q1}, [r5]! @load 16 Word16 x[]
67 VLD1.S16 {Q0, Q1}, [r5]! @load 16 Word16 x[]
68 VLD1.S16 {Q2, Q3}, [r5]! @load 16 Word16 x[]
69 VLD1.S16 {Q4, Q5}, [r5]! @load 16 Word16 x[]
70 VLD1.S16 {Q6, Q7}, [r5]! @load 16 Word16 x[]
/frameworks/av/media/libstagefright/codecs/mp3dec/src/asm/
Dpvmp3_mdct_18_gcc.s51 mov r5,r0
92 mov r0,r5 @@ r0 = vec
94 add r0,r5,#0x24 @@ r0 = &vec[9]
97 ldr r0,[r5,#0x20]
98 ldr r2,[r5,#0x40]
99 str r0,[r5,#0x40]
100 ldr r0,[r5,#0x1c]
101 ldr r3,[r5,#0x38]
102 str r0,[r5,#0x38]
103 ldr r1,[r5,#0x18]
[all …]
Dpvmp3_polyphase_filter_window_gcc.s69 ldr r5,[r3]
73 smlal r2,r9,lr,r5
77 smlal r5,r11,r2,r5
78 smull r6,r5,r2,r6
79 sub r9,r9,r5
80 ldr r5,[r1,#8]
83 smlal r6,r9,r5,r7
84 smull r6,r2,r5,r8
85 ldr r5,[r1,#0xc]
87 smlal r8,r9,r5,r8
[all …]
Dpvmp3_dct_16_gcc.s77 smull r4,r5,lr,r4
187 sub lr,r5,lr
189 add r3,r5,r3
190 smull r5,lr,r4,lr
192 ldr r5,[sp,#0x10]
194 sub r5,r5,r6
196 mov r5,r5,lsl #1
197 smull r7,r5,r6,r5
215 rsb r5,r5,#0
231 sub r4,lr,r5
[all …]
Dpvmp3_dct_9_gcc.s52 ldr r5,[r0,#8]
54 add r12,r4,r5
55 sub r4,r4,r5
56 ldr r5,[r0, #0x14]
59 add r6,r5,r7
60 sub r5,r5,r7
118 mov r1,r5,lsl #1
133 add r4,r5,r4
148 smull r5,lr,r4,lr
154 smull r5,lr,r7,r1
[all …]
/frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/
Dcor_h_vec_opt.s30 @r5 ---- cor_1[]
47 MOV r5, #0 @L_sum1 = 0
58 MLA r5, r12, r8, r5
64 MLA r5, r12, r14, r5
66 MOV r5, r5, LSL #2 @L_sum1 = (L_sum1 << 2)
68 ADD r9, r5, r14
69 MOV r5, r9, ASR #16
75 MUL r12, r5, r10
77 MOV r5, r12, ASR #15
85 ADD r5, r5, r10
[all …]
DNorm_Corr_opt.s31 @ r5 --- t_max
59 ADD r5, r0, r11, LSL #1 @get the &exc[k]
63 MOV r0, r5
72 MOV r5, #64
89 SUBS r5, r5, #8
104 MOV r5, #0 @L_tmp = 0
116 SMLABB r5, r10, r11, r5 @L_tmp += xn[i] * excf[i]
117 SMLATT r5, r10, r11, r5 @L_tmp += xn[i+1] * excf[i+1]
122 SMLABB r5, r10, r11, r5
123 SMLATT r5, r10, r11, r5
[all …]
Dconvolve_opt.s40 ADD r5, r3, #1 @ i = n + 1
44 SUB r5, r5, #1
48 CMP r5, #0
61 SUBS r5, r5, #4
68 ADD r5, r11, r8, LSL #1
69 MOV r5, r5, LSR #16 @extract_h(s)
71 STRH r5, [r2], #2 @y[n]
75 ADD r5, r3, #1
83 SUB r5, r5, #2
87 CMP r5, #0
[all …]
Dsyn_filt_opt.s40 MOV r5, r13 @ copy yy = y_buf address
56 STRH r6, [r5], #2
57 STRH r7, [r5], #2
58 STRH r8, [r5], #2
59 STRH r9, [r5], #2
60 STRH r10, [r5], #2
61 STRH r11, [r5], #2
62 STRH r12, [r5], #2
63 STRH r14, [r5], #2
74 STRH r6, [r5], #2
[all …]
Dscale_sig_opt.s44 LDRSH r5, [r4] @load x[i]
45 MOV r12, r5, LSL r10
46 TEQ r5, r12, ASR r10
47 EORNE r12, r8, r5, ASR #31
57 LDRSH r5, [r4] @load x[i]
58 MOV r6, r5, LSL #16 @L_tmp = x[i] << 16
59 MOV r5, r6, ASR r7 @L_tmp >>= exp
60 QADD r11, r5, r9
DSyn_filt_32_opt.s33 @ sig_lo[] --- r5
43 LDR r5, [r13, #44] @ get sig_lo[] address
97 LDRSH r6, [r5, #-2] @ load sig_lo[i-1]
98 LDRSH r7, [r5, #-4] @ load sig_lo[i-2]
101 LDRSH r9, [r5, #-6] @ load sig_lo[i-3]
102 LDRSH r10, [r5, #-8] @ load sig_lo[i-4]
106 LDRSH r6, [r5, #-10] @ load sig_lo[i-5]
109 LDRSH r7, [r5, #-12] @ load sig_lo[i-6]
111 LDRSH r9, [r5, #-14] @ load sig_lo[i-7]
114 LDRSH r10, [r5, #-16] @ load sig_lo[i-8]
[all …]
Dresidu_asm_opt.s35 LDRH r5, [r0], #2
37 ORR r5, r6, r5, LSL #16 @r5 --- a0, a1
80 SMULTB r3, r5, r2 @i1(0) --- r3 = x[0] * a0
81 SMULTT r4, r5, r2 @i2(0) --- r4 = x[1] * a0
82 SMULTB r11, r5, r10 @i3(0) --- r11 = x[2] * a0
83 SMULTT r12, r5, r10 @i4(0) --- r12 = x[3] * a0
85 SMLABB r4, r5, r2, r4 @i2(1) --- r4 += x[0] * a1
86 SMLABT r11, r5, r2, r11 @i3(1) --- r11 += x[1] * a0
87 SMLABB r12, r5, r10, r12 @i4(1) --- r12 += x[2] * a1
95 SMLABT r3, r5, r2, r3 @i1(1) --- r3 += x[-1] * a1
DDot_p_opt.s36 MOV r5, #0 @ i = 0
56 ADD r5, r5, #8
58 CMP r5, r2
DDeemph_32_opt.s40 LDR r5, =22282 @r5---mu
45 MOV r8, r5, ASR #1 @fac = mu >> 1
46 LDR r5, [r3]
49 MUL r9, r5, r8
DFilt_6k_7k_opt.s40 MOV r5, r2 @ copy mem[] address
85 STR r5, [sp, #-4] @ PUSH r5 to stack
87 @ not use registers: r4, r10, r12, r14, r5
89 MOV r5, #0 @ i = 0
166 ADD r5, r5, #1
170 CMP r5, #80
/frameworks/av/media/libstagefright/codecs/m4v_h263/dec/src/
Didct.cpp131 int32 r0, r1, r2, r3, r4, r5, r6, r7, r8; /* butterfly nodes */ in idct_intra() local
154 r5 = blk[B_SIZE * 7 + i]; in idct_intra()
158 if (!(r1 | r2 | r3 | r4 | r5 | r6 | r7)) in idct_intra()
182 r8 = W7 * (r4 + r5); in idct_intra()
186 r5 = (r8 - (W1 + W7) * r5); in idct_intra()
201 r6 = r5 + r7; in idct_intra()
202 r5 -= r7; in idct_intra()
209 r2 = (181 * (r4 + r5) + 128) >> 8; /* rounding */ in idct_intra()
210 r4 = (181 * (r4 - r5) + 128) >> 8; in idct_intra()
242 r5 = tmpBLK32[7+(i<<3)]; in idct_intra()
[all …]
/frameworks/rs/cpu_ref/
DrsCpuIntrinsics_neon_YuvToRGB.S89 movw r5, #((16 * 149 + (128 >> 1) + 128 * 204) >> 1)
90 vdup.i16 q13, r5
91 movw r5, #((-16 * 149 + 128 * 50 + 128 * 104) >> 0)
92 vdup.i16 q14, r5
93 movw r5, #((16 * 149 + (128 << 2) + 128 * 254) >> 1)
94 vdup.i16 q15, r5
227 push {r4,r5}
228 ldr r5, [sp, #8]
233 add r0, r5, LSL #2
234 add r1, r5
[all …]
DrsCpuIntrinsics_neon_Convolve.S42 mov r5, #8
46 vld1.8 {q13}, [r1], r5
47 vld1.8 {q14}, [r2], r5
48 vld1.8 {q15}, [r3], r5
51 pld [r1, r5]
52 pld [r2, r5]
53 pld [r3, r5]
126 ldr r5, [sp, #24 + 64]
236 vld1.8 {d24, d25, d26}, [r5], r7 @ y0 ( y + 2 )
239 pld [r5, r7]
/frameworks/base/core/tests/coretests/src/com/android/internal/os/
DBinderDeathDispatcherTest.java145 DeathRecipient r5 = mock(DeathRecipient.class); in testRegisterAndUnregister() local
208 DeathRecipient r5 = mock(DeathRecipient.class); in testRegisterAndKill() local
223 d.linkToDeath(t3, r5); in testRegisterAndKill()
234 verify(r5, times(0)).binderDied(); in testRegisterAndKill()
238 reset(r1, r2, r3, r4, r5); in testRegisterAndKill()
245 verify(r5, times(0)).binderDied(); in testRegisterAndKill()
249 reset(r1, r2, r3, r4, r5); in testRegisterAndKill()
256 verify(r5, times(1)).binderDied(); in testRegisterAndKill()

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