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Searched refs:S16 (Results 1 – 6 of 6) sorted by relevance

/art/runtime/arch/arm/
Dregisters_arm.h74 S16 = 16, enumerator
Dcallee_save_frame_arm.h52 (1 << art::arm::S16) | (1 << art::arm::S17) | (1 << art::arm::S18) | (1 << art::arm::S19) |
/art/runtime/arch/arm64/
Dregisters_arm64.h170 S16 = 16, enumerator
/art/compiler/optimizing/
Dcode_generator_vector_arm_vixl.cc184 __ Vneg(DataTypeValue::S16, dst, src); in VisitVecNeg()
211 __ Vabs(DataTypeValue::S16, dst, src); in VisitVecAbs()
324 __ Vqadd(DataTypeValue::S16, dst, lhs, rhs); in VisitVecSaturationAdd()
363 ? __ Vrhadd(DataTypeValue::S16, dst, lhs, rhs) in VisitVecHalvingAdd()
364 : __ Vhadd(DataTypeValue::S16, dst, lhs, rhs); in VisitVecHalvingAdd()
426 __ Vqsub(DataTypeValue::S16, dst, lhs, rhs); in VisitVecSaturationSub()
496 __ Vmin(DataTypeValue::S16, dst, lhs, rhs); in VisitVecMin()
536 __ Vmax(DataTypeValue::S16, dst, lhs, rhs); in VisitVecMax()
700 __ Vshr(DataTypeValue::S16, dst, lhs, value); in VisitVecShr()
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc80 ArmManagedRegister::FromSRegister(S16),
137 ArmManagedRegister::FromSRegister(S16),
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc561 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S16))); in TEST()
584 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S16))); in TEST()
722 EXPECT_TRUE(vixl::aarch64::s16.Is(Arm64Assembler::reg_s(S16))); in TEST()