1 /*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "arch/arm64/instruction_set_features_arm64.h"
18 #include "assembler_arm64.h"
19 #include "entrypoints/quick/quick_entrypoints.h"
20 #include "heap_poisoning.h"
21 #include "offsets.h"
22 #include "thread.h"
23
24 using namespace vixl::aarch64; // NOLINT(build/namespaces)
25
26 namespace art {
27 namespace arm64 {
28
29 #ifdef ___
30 #error "ARM64 Assembler macro already defined."
31 #else
32 #define ___ vixl_masm_.
33 #endif
34
35 // Sets vixl::CPUFeatures according to ART instruction set features.
SetVIXLCPUFeaturesFromART(vixl::aarch64::MacroAssembler * vixl_masm_,const Arm64InstructionSetFeatures * art_features)36 static void SetVIXLCPUFeaturesFromART(vixl::aarch64::MacroAssembler* vixl_masm_,
37 const Arm64InstructionSetFeatures* art_features) {
38 // Retrieve already initialized default features of vixl.
39 vixl::CPUFeatures* features = vixl_masm_->GetCPUFeatures();
40
41 DCHECK(features->Has(vixl::CPUFeatures::kFP));
42 DCHECK(features->Has(vixl::CPUFeatures::kNEON));
43 DCHECK(art_features != nullptr);
44 if (art_features->HasCRC()) {
45 features->Combine(vixl::CPUFeatures::kCRC32);
46 }
47 if (art_features->HasDotProd()) {
48 features->Combine(vixl::CPUFeatures::kDotProduct);
49 }
50 if (art_features->HasFP16()) {
51 features->Combine(vixl::CPUFeatures::kFPHalf);
52 features->Combine(vixl::CPUFeatures::kNEONHalf);
53 }
54 if (art_features->HasLSE()) {
55 features->Combine(vixl::CPUFeatures::kAtomics);
56 }
57 }
58
Arm64Assembler(ArenaAllocator * allocator,const Arm64InstructionSetFeatures * art_features)59 Arm64Assembler::Arm64Assembler(ArenaAllocator* allocator,
60 const Arm64InstructionSetFeatures* art_features)
61 : Assembler(allocator) {
62 if (art_features != nullptr) {
63 SetVIXLCPUFeaturesFromART(&vixl_masm_, art_features);
64 }
65 }
66
FinalizeCode()67 void Arm64Assembler::FinalizeCode() {
68 ___ FinalizeCode();
69 }
70
CodeSize() const71 size_t Arm64Assembler::CodeSize() const {
72 return vixl_masm_.GetSizeOfCodeGenerated();
73 }
74
CodeBufferBaseAddress() const75 const uint8_t* Arm64Assembler::CodeBufferBaseAddress() const {
76 return vixl_masm_.GetBuffer().GetStartAddress<const uint8_t*>();
77 }
78
FinalizeInstructions(const MemoryRegion & region)79 void Arm64Assembler::FinalizeInstructions(const MemoryRegion& region) {
80 // Copy the instructions from the buffer.
81 MemoryRegion from(vixl_masm_.GetBuffer()->GetStartAddress<void*>(), CodeSize());
82 region.CopyFrom(0, from);
83 }
84
LoadRawPtr(ManagedRegister m_dst,ManagedRegister m_base,Offset offs)85 void Arm64Assembler::LoadRawPtr(ManagedRegister m_dst, ManagedRegister m_base, Offset offs) {
86 Arm64ManagedRegister dst = m_dst.AsArm64();
87 Arm64ManagedRegister base = m_base.AsArm64();
88 CHECK(dst.IsXRegister() && base.IsXRegister());
89 // Remove dst and base form the temp list - higher level API uses IP1, IP0.
90 UseScratchRegisterScope temps(&vixl_masm_);
91 temps.Exclude(reg_x(dst.AsXRegister()), reg_x(base.AsXRegister()));
92 ___ Ldr(reg_x(dst.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value()));
93 }
94
JumpTo(ManagedRegister m_base,Offset offs,ManagedRegister m_scratch)95 void Arm64Assembler::JumpTo(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch) {
96 Arm64ManagedRegister base = m_base.AsArm64();
97 Arm64ManagedRegister scratch = m_scratch.AsArm64();
98 CHECK(base.IsXRegister()) << base;
99 CHECK(scratch.IsXRegister()) << scratch;
100 // Remove base and scratch form the temp list - higher level API uses IP1, IP0.
101 UseScratchRegisterScope temps(&vixl_masm_);
102 temps.Exclude(reg_x(base.AsXRegister()), reg_x(scratch.AsXRegister()));
103 ___ Ldr(reg_x(scratch.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value()));
104 ___ Br(reg_x(scratch.AsXRegister()));
105 }
106
SpillRegisters(CPURegList registers,int offset)107 void Arm64Assembler::SpillRegisters(CPURegList registers, int offset) {
108 int size = registers.GetRegisterSizeInBytes();
109 const Register sp = vixl_masm_.StackPointer();
110 // Since we are operating on register pairs, we would like to align on
111 // double the standard size; on the other hand, we don't want to insert
112 // an extra store, which will happen if the number of registers is even.
113 if (!IsAlignedParam(offset, 2 * size) && registers.GetCount() % 2 != 0) {
114 const CPURegister& dst0 = registers.PopLowestIndex();
115 ___ Str(dst0, MemOperand(sp, offset));
116 cfi_.RelOffset(DWARFReg(dst0), offset);
117 offset += size;
118 }
119 while (registers.GetCount() >= 2) {
120 const CPURegister& dst0 = registers.PopLowestIndex();
121 const CPURegister& dst1 = registers.PopLowestIndex();
122 ___ Stp(dst0, dst1, MemOperand(sp, offset));
123 cfi_.RelOffset(DWARFReg(dst0), offset);
124 cfi_.RelOffset(DWARFReg(dst1), offset + size);
125 offset += 2 * size;
126 }
127 if (!registers.IsEmpty()) {
128 const CPURegister& dst0 = registers.PopLowestIndex();
129 ___ Str(dst0, MemOperand(sp, offset));
130 cfi_.RelOffset(DWARFReg(dst0), offset);
131 }
132 DCHECK(registers.IsEmpty());
133 }
134
UnspillRegisters(CPURegList registers,int offset)135 void Arm64Assembler::UnspillRegisters(CPURegList registers, int offset) {
136 int size = registers.GetRegisterSizeInBytes();
137 const Register sp = vixl_masm_.StackPointer();
138 // Be consistent with the logic for spilling registers.
139 if (!IsAlignedParam(offset, 2 * size) && registers.GetCount() % 2 != 0) {
140 const CPURegister& dst0 = registers.PopLowestIndex();
141 ___ Ldr(dst0, MemOperand(sp, offset));
142 cfi_.Restore(DWARFReg(dst0));
143 offset += size;
144 }
145 while (registers.GetCount() >= 2) {
146 const CPURegister& dst0 = registers.PopLowestIndex();
147 const CPURegister& dst1 = registers.PopLowestIndex();
148 ___ Ldp(dst0, dst1, MemOperand(sp, offset));
149 cfi_.Restore(DWARFReg(dst0));
150 cfi_.Restore(DWARFReg(dst1));
151 offset += 2 * size;
152 }
153 if (!registers.IsEmpty()) {
154 const CPURegister& dst0 = registers.PopLowestIndex();
155 ___ Ldr(dst0, MemOperand(sp, offset));
156 cfi_.Restore(DWARFReg(dst0));
157 }
158 DCHECK(registers.IsEmpty());
159 }
160
PoisonHeapReference(Register reg)161 void Arm64Assembler::PoisonHeapReference(Register reg) {
162 DCHECK(reg.IsW());
163 // reg = -reg.
164 ___ Neg(reg, Operand(reg));
165 }
166
UnpoisonHeapReference(Register reg)167 void Arm64Assembler::UnpoisonHeapReference(Register reg) {
168 DCHECK(reg.IsW());
169 // reg = -reg.
170 ___ Neg(reg, Operand(reg));
171 }
172
MaybePoisonHeapReference(Register reg)173 void Arm64Assembler::MaybePoisonHeapReference(Register reg) {
174 if (kPoisonHeapReferences) {
175 PoisonHeapReference(reg);
176 }
177 }
178
MaybeUnpoisonHeapReference(Register reg)179 void Arm64Assembler::MaybeUnpoisonHeapReference(Register reg) {
180 if (kPoisonHeapReferences) {
181 UnpoisonHeapReference(reg);
182 }
183 }
184
GenerateMarkingRegisterCheck(Register temp,int code)185 void Arm64Assembler::GenerateMarkingRegisterCheck(Register temp, int code) {
186 // The Marking Register is only used in the Baker read barrier configuration.
187 DCHECK(kEmitCompilerReadBarrier);
188 DCHECK(kUseBakerReadBarrier);
189
190 vixl::aarch64::Register mr = reg_x(MR); // Marking Register.
191 vixl::aarch64::Register tr = reg_x(TR); // Thread Register.
192 vixl::aarch64::Label mr_is_ok;
193
194 // temp = self.tls32_.is.gc_marking
195 ___ Ldr(temp, MemOperand(tr, Thread::IsGcMarkingOffset<kArm64PointerSize>().Int32Value()));
196 // Check that mr == self.tls32_.is.gc_marking.
197 ___ Cmp(mr.W(), temp);
198 ___ B(eq, &mr_is_ok);
199 ___ Brk(code);
200 ___ Bind(&mr_is_ok);
201 }
202
203 #undef ___
204
205 } // namespace arm64
206 } // namespace art
207