Lines Matching full:reset

1 CPU Reset
10 document which provides greater implementation details around the reset code,
13 General reset code flow
16 The TF-A reset code is implemented in BL1 by default. The following high-level
19 |Default reset code flow|
21 This diagram shows the default, unoptimised reset flow. Depending on the system
29    this case. Please refer to section 6 "Using BL31 entrypoint as the reset
32 Programmable CPU reset address
35 By default, TF-A assumes that the CPU reset address is not programmable.
37 they reset. Further logic is then required to identify whether it is a cold or
40 If the reset vector address (reflected in the reset vector base address register
42 at the right address, both on a cold and warm reset. Therefore, the boot type
45 |Reset code flow with programmable reset address|
48 This option only affects the TF-A reset image, which is BL1 by default or BL31 if
51 On both the FVP and Juno platforms, the reset vector address is not programmable
57 By default, TF-A assumes that several CPUs may be released out of reset.
67 |Reset code flow with single CPU released out of reset|
70 option only affects the TF-A reset image, which is BL1 by default or BL31 if
75 reset. Therefore, both platform ports use ``COLD_BOOT_SINGLE_CPU=0``.
77 Programmable CPU reset address, Cold boot on a single CPU
81 a programmable CPU reset address and which release a single CPU out of reset.
85 |Reset code flow with programmable reset address and single CPU released out of reset|
88 and ``PROGRAMMABLE_RESET_ADDRESS=1``. These options only affect the TF-A reset
91 Using BL31 entrypoint as the reset address
98 to always reset to BL31 which eliminates the need for BL1 and BL2.
105 reset vector base address, before the application processor is powered on.
110 Although the Arm FVP platform does not support programming the reset base
117 SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run
121 Although technically it would be possible to program the reset base address with
131 In this configuration, BL31 uses the same reset framework and code as the one
136 In the default, unoptimised BL31 reset flow, on a warm boot a CPU is directed
158 .. |Default reset code flow| image:: ../resources/diagrams/default_reset_code.png
159 .. |Reset code flow with programmable reset address| image:: ../resources/diagrams/reset_code_no_bo…
160 .. |Reset code flow with single CPU released out of reset| image:: ../resources/diagrams/reset_code…
161 .. |Reset code flow with programmable reset address and single CPU released out of reset| image:: .…