1369 				    uint32_t *pllcfg, int plloff)  in stm32mp1_check_pll_conf()  argument
1396 		 (pllcfg[PLLCFG_M] + 1U);  in stm32mp1_check_pll_conf()
1407 	value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &  in stm32mp1_check_pll_conf()
1409 	value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &  in stm32mp1_check_pll_conf()
1429 	value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &  in stm32mp1_check_pll_conf()
1431 	value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &  in stm32mp1_check_pll_conf()
1433 	value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &  in stm32mp1_check_pll_conf()
1502 				       uint32_t *pllcfg)  in stm32mp1_pll_config_output()  argument
1508 	value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &  in stm32mp1_pll_config_output()
1510 	value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &  in stm32mp1_pll_config_output()
1512 	value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &  in stm32mp1_pll_config_output()
1518 			       uint32_t *pllcfg, uint32_t fracv)  in stm32mp1_pll_config()  argument
1531 		 (pllcfg[PLLCFG_M] + 1U);  in stm32mp1_pll_config()
1542 	value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &  in stm32mp1_pll_config()
1544 	value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &  in stm32mp1_pll_config()
1560 	stm32mp1_pll_config_output(pll_id, pllcfg);  in stm32mp1_pll_config()
1728 	unsigned int pllcfg[_PLL_NB][PLLCFG_NB];  in stm32mp1_clk_init()  local
1771 					    (int)PLLCFG_NB, pllcfg[i]);  in stm32mp1_clk_init()
1830 							pllcfg[_PLL3],  in stm32mp1_clk_init()
1834 							pllcfg[_PLL4],  in stm32mp1_clk_init()
1932 			stm32mp1_pll_config_output(i, pllcfg[i]);  in stm32mp1_clk_init()
1938 		ret = stm32mp1_pll_config(i, pllcfg[i], fracv);  in stm32mp1_clk_init()
1958 		ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]);  in stm32mp1_clk_init()