655 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_rcc_is_secure()  local
658 	return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;  in stm32mp1_rcc_is_secure()
663 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_rcc_is_mckprot()  local
666 	return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;  in stm32mp1_rcc_is_mckprot()
720 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_clk_get_parent()  local
747 	p_sel = (mmio_read_32(rcc_base + sel->offset) &  in stm32mp1_clk_get_parent()
774 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_pll_get_fvco()  local
776 	cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1);  in stm32mp1_pll_get_fvco()
777 	fracr = mmio_read_32(rcc_base + pll->pllxfracr);  in stm32mp1_pll_get_fvco()
829 	uintptr_t rcc_base = stm32mp_rcc_base();  in get_clock_rate()  local
834 		reg = mmio_read_32(rcc_base + RCC_MPCKSELR);  in get_clock_rate()
848 			reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);  in get_clock_rate()
864 		reg = mmio_read_32(rcc_base + RCC_ASSCKSELR);  in get_clock_rate()
880 		reg = mmio_read_32(rcc_base + RCC_AXIDIVR);  in get_clock_rate()
885 			reg = mmio_read_32(rcc_base + RCC_APB4DIVR);  in get_clock_rate()
889 			reg = mmio_read_32(rcc_base + RCC_APB5DIVR);  in get_clock_rate()
901 		reg = mmio_read_32(rcc_base + RCC_MSSCKSELR);  in get_clock_rate()
920 		reg = mmio_read_32(rcc_base + RCC_MCUDIVR);  in get_clock_rate()
925 			reg = mmio_read_32(rcc_base + RCC_APB1DIVR);  in get_clock_rate()
929 			reg = mmio_read_32(rcc_base + RCC_APB2DIVR);  in get_clock_rate()
933 			reg = mmio_read_32(rcc_base + RCC_APB3DIVR);  in get_clock_rate()
942 		reg = mmio_read_32(rcc_base + RCC_CPERCKSELR);  in get_clock_rate()
1028 	uintptr_t rcc_base = stm32mp_rcc_base();  in __clk_enable()  local
1033 		mmio_write_32(rcc_base + gate->offset, BIT(gate->bit));  in __clk_enable()
1035 		mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit));  in __clk_enable()
1041 	uintptr_t rcc_base = stm32mp_rcc_base();  in __clk_disable()  local
1046 		mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET,  in __clk_disable()
1049 		mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit));  in __clk_disable()
1055 	uintptr_t rcc_base = stm32mp_rcc_base();  in __clk_is_enabled()  local
1057 	return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit);  in __clk_is_enabled()
1234 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_lse_enable()  local
1237 		mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);  in stm32mp1_lse_enable()
1241 		mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP);  in stm32mp1_lse_enable()
1248 	value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>  in stm32mp1_lse_enable()
1258 		mmio_clrsetbits_32(rcc_base + RCC_BDCR,  in stm32mp1_lse_enable()
1284 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_hse_enable()  local
1287 		mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP);  in stm32mp1_hse_enable()
1291 		mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP);  in stm32mp1_hse_enable()
1300 		mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);  in stm32mp1_hse_enable()
1323 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_set_hsidiv()  local
1324 	uintptr_t address = rcc_base + RCC_OCRDYR;  in stm32mp1_set_hsidiv()
1326 	mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,  in stm32mp1_set_hsidiv()
1372 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_check_pll_conf()  local
1373 	uintptr_t pllxcr = rcc_base + pll->pllxcr;  in stm32mp1_check_pll_conf()
1375 	uintptr_t clksrc_address = rcc_base + (clksrc >> 4);  in stm32mp1_check_pll_conf()
1393 	src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK;  in stm32mp1_check_pll_conf()
1413 	if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) {  in stm32mp1_check_pll_conf()
1424 	if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {  in stm32mp1_check_pll_conf()
1435 	if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) {  in stm32mp1_check_pll_conf()
1505 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_pll_config_output()  local
1514 	mmio_write_32(rcc_base + pll->pllxcfgr2, value);  in stm32mp1_pll_config_output()
1521 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_pll_config()  local
1527 	src = mmio_read_32(rcc_base + pll->rckxselr) &  in stm32mp1_pll_config()
1548 	mmio_write_32(rcc_base + pll->pllxcfgr1, value);  in stm32mp1_pll_config()
1552 	mmio_write_32(rcc_base + pll->pllxfracr, value);  in stm32mp1_pll_config()
1555 	mmio_write_32(rcc_base + pll->pllxfracr, value);  in stm32mp1_pll_config()
1558 	mmio_write_32(rcc_base + pll->pllxfracr, value);  in stm32mp1_pll_config()
1725 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_clk_init()  local
1745 		mmio_write_32(rcc_base + RCC_TZCR, 0);  in stm32mp1_clk_init()
1826 	if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) &  in stm32mp1_clk_init()
1861 	mmio_write_32(rcc_base + RCC_MPCKDIVR,  in stm32mp1_clk_init()
1863 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);  in stm32mp1_clk_init()
1867 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);  in stm32mp1_clk_init()
1871 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);  in stm32mp1_clk_init()
1875 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR);  in stm32mp1_clk_init()
1879 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);  in stm32mp1_clk_init()
1883 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);  in stm32mp1_clk_init()
1887 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);  in stm32mp1_clk_init()
1893 	mmio_write_32(rcc_base + RCC_RTCDIVR,  in stm32mp1_clk_init()
2017 	mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR,  in stm32mp1_clk_init()
2054 	uintptr_t rcc_base = stm32mp_rcc_base();  in get_parent_id_parent()  local
2101 		p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) &  in get_parent_id_parent()
2110 		p_sel = mmio_read_32(rcc_base + pll->rckxselr) &  in get_parent_id_parent()