Lines Matching full:08
27 printf("\tInit 0x%08X Value 0x%08X\n", r[0], r[1]); in dump_timer()
62 printf("Descriptor Address 0x%08X%08X\n", in dump_queue()
64 printf("Address Counter 0x%08X%08X\n", in dump_queue()
67 printf("BMU Control/Status 0x%08X\n", d->csr); in dump_queue()
68 printf("Flag & FIFO Address 0x%08X\n", d->flag); in dump_queue()
70 printf("Control 0x%08X\n", d->ctl); in dump_queue()
71 printf("Next 0x%08X\n", d->next); in dump_queue()
72 printf("Data 0x%08X%08X\n", in dump_queue()
74 printf("Status 0x%08X\n", d->status); in dump_queue()
75 printf("Timestamp 0x%08X\n", d->timestamp); in dump_queue()
98 printf("Start Address 0x%08X\n", r[0]); in dump_ram()
99 printf("End Address 0x%08X\n", r[1]); in dump_ram()
100 printf("Write Pointer 0x%08X\n", r[2]); in dump_ram()
101 printf("Read Pointer 0x%08X\n", r[3]); in dump_ram()
104 printf("Upper Threshold/Pause Packets 0x%08X\n", r[4]); in dump_ram()
105 printf("Lower Threshold/Pause Packets 0x%08X\n", r[5]); in dump_ram()
106 printf("Upper Threshold/High Priority 0x%08X\n", r[6]); in dump_ram()
107 printf("Lower Threshold/High Priority 0x%08X\n", r[7]); in dump_ram()
109 printf("Packet Counter 0x%08X\n", r[8]); in dump_ram()
110 printf("Level 0x%08X\n", r[9]); in dump_ram()
111 printf("Control 0x%08X\n", r[10]); in dump_ram()
120 printf("End Address 0x%08X\n", r[0]); in dump_fifo()
121 printf("Write Pointer 0x%08X\n", r[1]); in dump_fifo()
122 printf("Read Pointer 0x%08X\n", r[2]); in dump_fifo()
123 printf("Packet Counter 0x%08X\n", r[3]); in dump_fifo()
124 printf("Level 0x%08X\n", r[4]); in dump_fifo()
125 printf("Control 0x%08X\n", r[5]); in dump_fifo()
126 printf("Control/Test 0x%08X\n", r[6]); in dump_fifo()
152 printf("%-32s 0x%08X\n", regs[i], r[i]); in dump_gmac_fifo()
248 printf("LED Control/Status 0x%08X\n", *(u32 *) (r + 4)); in dump_control()
250 printf("Interrupt Source 0x%08X\n", *(u32 *) (r + 8)); in dump_control()
251 printf("Interrupt Mask 0x%08X\n", *(u32 *) (r + 0xc)); in dump_control()
252 printf("Interrupt Hardware Error Source 0x%08X\n", *(u32 *) (r + 0x10)); in dump_control()
253 printf("Interrupt Hardware Error Mask 0x%08X\n", *(u32 *) (r + 0x14)); in dump_control()
254 printf("Interrupt Control 0x%08X\n", *(u32 *) (r + 0x2c)); in dump_control()
255 printf("Interrupt Moderation Mask 0x%08X\n", *(u32 *) (r + 0x14c)); in dump_control()
256 printf("Hardware Moderation Mask 0x%08X\n", *(u32 *) (r + 0x150)); in dump_control()
259 printf("General Purpose I/O 0x%08X\n", *(u32 *) (r + 0x15c)); in dump_control()
274 printf("CSR Receive Queue 1 0x%08X\n", r[24]); in skge_dump_regs()
275 printf("CSR Sync Queue 1 0x%08X\n", r[26]); in skge_dump_regs()
276 printf("CSR Async Queue 1 0x%08X\n", r[27]); in skge_dump_regs()
278 printf("CSR Receive Queue 2 0x%08X\n", r[25]); in skge_dump_regs()
279 printf("CSR Async Queue 2 0x%08X\n", r[29]); in skge_dump_regs()
280 printf("CSR Sync Queue 2 0x%08X\n", r[28]); in skge_dump_regs()
346 printf("Descriptor Address 0x%08X%08X\n", in dump_queue2()
348 printf("Status 0x%08X\n", d->status); in dump_queue2()
349 printf("Timestamp 0x%08X\n", d->timestamp); in dump_queue2()
350 printf("BMU Control/Status 0x%08X\n", d->csr); in dump_queue2()
352 printf("Request 0x%08X%08X\n", in dump_queue2()
369 printf("Control 0x%08X\n", reg[0]); in dump_prefetch()
371 printf("Start Address 0x%08x%08x\n", reg[3], reg[2]); in dump_prefetch()
396 printf("CSR Receive Queue 1 0x%08X\n", r32[24]); in sky2_dump_regs()
397 printf("CSR Sync Queue 1 0x%08X\n", r32[26]); in sky2_dump_regs()
398 printf("CSR Async Queue 1 0x%08X\n", r32[27]); in sky2_dump_regs()
402 printf("CSR Receive Queue 2 0x%08X\n", r32[25]); in sky2_dump_regs()
403 printf("CSR Async Queue 2 0x%08X\n", r32[29]); in sky2_dump_regs()
404 printf("CSR Sync Queue 2 0x%08X\n", r32[28]); in sky2_dump_regs()