Lines Matching refs:DEFINEREG2
779 #define DEFINEREG2(reg, func) \ macro
789 DEFINEREG2(DCC, i830_debug_dcc),
790 DEFINEREG2(CHDECMISC, i830_debug_chdecmisc),
806 DEFINEREG2(VCLK_DIVISOR_VGA0, i830_debug_fp),
807 DEFINEREG2(VCLK_DIVISOR_VGA1, i830_debug_fp),
808 DEFINEREG2(VCLK_POST_DIV, i830_debug_vga_pd),
809 DEFINEREG2(DPLL_TEST, i830_debug_dpll_test),
812 DEFINEREG2(DSPCLK_GATE_D, i830_debug_dspclk_gate_d),
816 DEFINEREG2(SDVOB, i830_debug_sdvo),
817 DEFINEREG2(SDVOC, i830_debug_sdvo),
829 DEFINEREG2(ADPA, i830_debug_adpa),
830 DEFINEREG2(LVDS, i830_debug_lvds),
831 DEFINEREG2(DVOA, i830_debug_dvo),
832 DEFINEREG2(DVOB, i830_debug_dvo),
833 DEFINEREG2(DVOC, i830_debug_dvo),
841 DEFINEREG2(PP_CONTROL, i830_debug_pp_control),
842 DEFINEREG2(PP_STATUS, i830_debug_pp_status),
851 DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
852 DEFINEREG2(DSPASTRIDE, i830_debug_dspstride),
853 DEFINEREG2(DSPAPOS, i830_debug_xy),
854 DEFINEREG2(DSPASIZE, i830_debug_xyminus1),
858 DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
859 DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
860 DEFINEREG2(PIPEASTAT, i830_debug_pipestat),
869 DEFINEREG2(FPA0, i830_debug_fp),
870 DEFINEREG2(FPA1, i830_debug_fp),
871 DEFINEREG2(DPLL_A, i830_debug_dpll),
873 DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
874 DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
875 DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
876 DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
877 DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
878 DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
882 DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
883 DEFINEREG2(DSPBSTRIDE, i830_debug_dspstride),
884 DEFINEREG2(DSPBPOS, i830_debug_xy),
885 DEFINEREG2(DSPBSIZE, i830_debug_xyminus1),
889 DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
890 DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
891 DEFINEREG2(PIPEBSTAT, i830_debug_pipestat),
900 DEFINEREG2(FPB0, i830_debug_fp),
901 DEFINEREG2(FPB1, i830_debug_fp),
902 DEFINEREG2(DPLL_B, i830_debug_dpll),
904 DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
905 DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
906 DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
907 DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
908 DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
909 DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
916 DEFINEREG2(VGACNTRL, i830_debug_vgacntrl),
2100 DEFINEREG2(CPU_VGACNTRL, i830_debug_vgacntrl),
2103 DEFINEREG2(RR_HW_CTL, ironlake_debug_rr_hw_ctl),
2117 DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
2119 DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
2120 DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
2121 DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
2122 DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
2123 DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
2124 DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
2126 DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
2128 DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu),
2129 DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n),
2130 DEFINEREG2(PIPEA_DATA_M2, ironlake_debug_m_tu),
2131 DEFINEREG2(PIPEA_DATA_N2, ironlake_debug_n),
2133 DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n),
2134 DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n),
2135 DEFINEREG2(PIPEA_LINK_M2, ironlake_debug_n),
2136 DEFINEREG2(PIPEA_LINK_N2, ironlake_debug_n),
2138 DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
2140 DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride),
2142 DEFINEREG2(DSPATILEOFF, i830_debug_xy),
2146 DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
2148 DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
2149 DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
2150 DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
2151 DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
2152 DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
2153 DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
2155 DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
2157 DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
2158 DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
2159 DEFINEREG2(PIPEB_DATA_M2, ironlake_debug_m_tu),
2160 DEFINEREG2(PIPEB_DATA_N2, ironlake_debug_n),
2162 DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
2163 DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
2164 DEFINEREG2(PIPEB_LINK_M2, ironlake_debug_n),
2165 DEFINEREG2(PIPEB_LINK_N2, ironlake_debug_n),
2167 DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
2169 DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
2171 DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
2175 DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
2177 DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
2178 DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
2179 DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
2180 DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
2181 DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
2182 DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
2184 DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
2186 DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
2187 DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
2188 DEFINEREG2(PIPEC_DATA_M2, ironlake_debug_m_tu),
2189 DEFINEREG2(PIPEC_DATA_N2, ironlake_debug_n),
2191 DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
2192 DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
2193 DEFINEREG2(PIPEC_LINK_M2, ironlake_debug_n),
2194 DEFINEREG2(PIPEC_LINK_N2, ironlake_debug_n),
2196 DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
2198 DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
2200 DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
2204 DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
2205 DEFINEREG2(PFA_CTL_2, ironlake_debug_panel_fitting_2),
2206 DEFINEREG2(PFA_CTL_3, ironlake_debug_panel_fitting_3),
2207 DEFINEREG2(PFA_CTL_4, ironlake_debug_panel_fitting_4),
2208 DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
2209 DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
2210 DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
2211 DEFINEREG2(PFB_CTL_2, ironlake_debug_panel_fitting_2),
2212 DEFINEREG2(PFB_CTL_3, ironlake_debug_panel_fitting_3),
2213 DEFINEREG2(PFB_CTL_4, ironlake_debug_panel_fitting_4),
2214 DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
2215 DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
2216 DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting),
2217 DEFINEREG2(PFC_CTL_2, ironlake_debug_panel_fitting_2),
2218 DEFINEREG2(PFC_CTL_3, ironlake_debug_panel_fitting_3),
2219 DEFINEREG2(PFC_CTL_4, ironlake_debug_panel_fitting_4),
2220 DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
2221 DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
2225 DEFINEREG2(PCH_DREF_CONTROL, ironlake_debug_dref_ctl),
2226 DEFINEREG2(PCH_RAWCLK_FREQ, ironlake_debug_rawclk_freq),
2230 DEFINEREG2(PCH_DPLL_SEL, snb_debug_dpll_sel),
2233 DEFINEREG2(PCH_DPLL_A, ironlake_debug_pch_dpll),
2234 DEFINEREG2(PCH_DPLL_B, ironlake_debug_pch_dpll),
2235 DEFINEREG2(PCH_FPA0, i830_debug_fp),
2236 DEFINEREG2(PCH_FPA1, i830_debug_fp),
2237 DEFINEREG2(PCH_FPB0, i830_debug_fp),
2238 DEFINEREG2(PCH_FPB1, i830_debug_fp),
2240 DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
2241 DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
2242 DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
2243 DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
2244 DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
2245 DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
2248 DEFINEREG2(TRANSA_DATA_M1, ironlake_debug_m_tu),
2249 DEFINEREG2(TRANSA_DATA_N1, ironlake_debug_n),
2250 DEFINEREG2(TRANSA_DATA_M2, ironlake_debug_m_tu),
2251 DEFINEREG2(TRANSA_DATA_N2, ironlake_debug_n),
2252 DEFINEREG2(TRANSA_DP_LINK_M1, ironlake_debug_n),
2253 DEFINEREG2(TRANSA_DP_LINK_N1, ironlake_debug_n),
2254 DEFINEREG2(TRANSA_DP_LINK_M2, ironlake_debug_n),
2255 DEFINEREG2(TRANSA_DP_LINK_N2, ironlake_debug_n),
2257 DEFINEREG2(TRANS_HTOTAL_B, i830_debug_hvtotal),
2258 DEFINEREG2(TRANS_HBLANK_B, i830_debug_hvsyncblank),
2259 DEFINEREG2(TRANS_HSYNC_B, i830_debug_hvsyncblank),
2260 DEFINEREG2(TRANS_VTOTAL_B, i830_debug_hvtotal),
2261 DEFINEREG2(TRANS_VBLANK_B, i830_debug_hvsyncblank),
2262 DEFINEREG2(TRANS_VSYNC_B, i830_debug_hvsyncblank),
2265 DEFINEREG2(TRANSB_DATA_M1, ironlake_debug_m_tu),
2266 DEFINEREG2(TRANSB_DATA_N1, ironlake_debug_n),
2267 DEFINEREG2(TRANSB_DATA_M2, ironlake_debug_m_tu),
2268 DEFINEREG2(TRANSB_DATA_N2, ironlake_debug_n),
2269 DEFINEREG2(TRANSB_DP_LINK_M1, ironlake_debug_n),
2270 DEFINEREG2(TRANSB_DP_LINK_N1, ironlake_debug_n),
2271 DEFINEREG2(TRANSB_DP_LINK_M2, ironlake_debug_n),
2272 DEFINEREG2(TRANSB_DP_LINK_N2, ironlake_debug_n),
2274 DEFINEREG2(TRANS_HTOTAL_C, i830_debug_hvtotal),
2275 DEFINEREG2(TRANS_HBLANK_C, i830_debug_hvsyncblank),
2276 DEFINEREG2(TRANS_HSYNC_C, i830_debug_hvsyncblank),
2277 DEFINEREG2(TRANS_VTOTAL_C, i830_debug_hvtotal),
2278 DEFINEREG2(TRANS_VBLANK_C, i830_debug_hvsyncblank),
2279 DEFINEREG2(TRANS_VSYNC_C, i830_debug_hvsyncblank),
2282 DEFINEREG2(TRANSC_DATA_M1, ironlake_debug_m_tu),
2283 DEFINEREG2(TRANSC_DATA_N1, ironlake_debug_n),
2284 DEFINEREG2(TRANSC_DATA_M2, ironlake_debug_m_tu),
2285 DEFINEREG2(TRANSC_DATA_N2, ironlake_debug_n),
2286 DEFINEREG2(TRANSC_DP_LINK_M1, ironlake_debug_n),
2287 DEFINEREG2(TRANSC_DP_LINK_N1, ironlake_debug_n),
2288 DEFINEREG2(TRANSC_DP_LINK_M2, ironlake_debug_n),
2289 DEFINEREG2(TRANSC_DP_LINK_N2, ironlake_debug_n),
2291 DEFINEREG2(TRANSACONF, ironlake_debug_transconf),
2292 DEFINEREG2(TRANSBCONF, ironlake_debug_transconf),
2293 DEFINEREG2(TRANSCCONF, ironlake_debug_transconf),
2295 DEFINEREG2(FDI_TXA_CTL, ironlake_debug_fdi_tx_ctl),
2296 DEFINEREG2(FDI_TXB_CTL, ironlake_debug_fdi_tx_ctl),
2297 DEFINEREG2(FDI_TXC_CTL, ironlake_debug_fdi_tx_ctl),
2298 DEFINEREG2(FDI_RXA_CTL, ironlake_debug_fdi_rx_ctl),
2299 DEFINEREG2(FDI_RXB_CTL, ironlake_debug_fdi_rx_ctl),
2300 DEFINEREG2(FDI_RXC_CTL, ironlake_debug_fdi_rx_ctl),
2312 DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
2313 DEFINEREG2(FDI_RXB_MISC, ironlake_debug_fdi_rx_misc),
2314 DEFINEREG2(FDI_RXC_MISC, ironlake_debug_fdi_rx_misc),
2330 DEFINEREG2(PCH_ADPA, i830_debug_adpa),
2331 DEFINEREG2(HDMIB, ironlake_debug_hdmi),
2332 DEFINEREG2(HDMIC, ironlake_debug_hdmi),
2333 DEFINEREG2(HDMID, ironlake_debug_hdmi),
2334 DEFINEREG2(PCH_LVDS, i830_debug_lvds),
2340 DEFINEREG2(DP_BUFTRANS(0), ironlake_debug_dp_buftrans),
2341 DEFINEREG2(DP_BUFTRANS(1), ironlake_debug_dp_buftrans),
2342 DEFINEREG2(DP_BUFTRANS(2), ironlake_debug_dp_buftrans),
2343 DEFINEREG2(DP_BUFTRANS(3), ironlake_debug_dp_buftrans),
2344 DEFINEREG2(DP_BUFTRANS(4), ironlake_debug_dp_buftrans),
2345 DEFINEREG2(DP_BUFTRANS(5), ironlake_debug_dp_buftrans),
2346 DEFINEREG2(DP_BUFTRANS(6), ironlake_debug_dp_buftrans),
2347 DEFINEREG2(DP_BUFTRANS(7), ironlake_debug_dp_buftrans),
2348 DEFINEREG2(DP_BUFTRANS(8), ironlake_debug_dp_buftrans),
2349 DEFINEREG2(DP_BUFTRANS(9), ironlake_debug_dp_buftrans),
2351 DEFINEREG2(TRANS_DP_CTL_A, snb_debug_trans_dp_ctl),
2352 DEFINEREG2(TRANS_DP_CTL_B, snb_debug_trans_dp_ctl),
2353 DEFINEREG2(TRANS_DP_CTL_C, snb_debug_trans_dp_ctl),
2355 DEFINEREG2(BLC_PWM_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
2356 DEFINEREG2(BLC_PWM_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
2357 DEFINEREG2(BLC_PWM_PCH_CTL1, ibx_debug_blc_pwm_ctl1),
2358 DEFINEREG2(BLC_PWM_PCH_CTL2, ibx_debug_blc_pwm_ctl2),
2360 DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status),
2361 DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control),
2366 DEFINEREG2(PORT_DBG, ivb_debug_port),
2383 DEFINEREG2(PIPE_DDI_FUNC_CTL_A, hsw_debug_pipe_ddi_func_ctl),
2384 DEFINEREG2(PIPE_DDI_FUNC_CTL_B, hsw_debug_pipe_ddi_func_ctl),
2385 DEFINEREG2(PIPE_DDI_FUNC_CTL_C, hsw_debug_pipe_ddi_func_ctl),
2386 DEFINEREG2(PIPE_DDI_FUNC_CTL_EDP, hsw_debug_pipe_ddi_func_ctl),
2402 DEFINEREG2(DDI_BUF_CTL_A, hsw_debug_ddi_buf_ctl),
2403 DEFINEREG2(DDI_BUF_CTL_B, hsw_debug_ddi_buf_ctl),
2404 DEFINEREG2(DDI_BUF_CTL_C, hsw_debug_ddi_buf_ctl),
2405 DEFINEREG2(DDI_BUF_CTL_D, hsw_debug_ddi_buf_ctl),
2406 DEFINEREG2(DDI_BUF_CTL_E, hsw_debug_ddi_buf_ctl),
2415 DEFINEREG2(PORT_CLK_SEL_A, hsw_debug_port_clk_sel),
2416 DEFINEREG2(PORT_CLK_SEL_B, hsw_debug_port_clk_sel),
2417 DEFINEREG2(PORT_CLK_SEL_C, hsw_debug_port_clk_sel),
2418 DEFINEREG2(PORT_CLK_SEL_D, hsw_debug_port_clk_sel),
2419 DEFINEREG2(PORT_CLK_SEL_E, hsw_debug_port_clk_sel),
2422 DEFINEREG2(PIPE_CLK_SEL_A, hsw_debug_pipe_clk_sel),
2423 DEFINEREG2(PIPE_CLK_SEL_B, hsw_debug_pipe_clk_sel),
2424 DEFINEREG2(PIPE_CLK_SEL_C, hsw_debug_pipe_clk_sel),
2427 DEFINEREG2(WM_PIPE_A, hsw_debug_wm_pipe),
2428 DEFINEREG2(WM_PIPE_B, hsw_debug_wm_pipe),
2429 DEFINEREG2(WM_PIPE_C, hsw_debug_wm_pipe),
2430 DEFINEREG2(WM_LP1, hsw_debug_lp_wm),
2431 DEFINEREG2(WM_LP2, hsw_debug_lp_wm),
2432 DEFINEREG2(WM_LP3, hsw_debug_lp_wm),
2444 DEFINEREG2(SFUSE_STRAP, hsw_debug_sfuse_strap),
2447 DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
2448 DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
2449 DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride),
2451 DEFINEREG2(DSPATILEOFF, i830_debug_xy),
2454 DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
2455 DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
2456 DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
2458 DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
2461 DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
2462 DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
2463 DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
2465 DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
2468 DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
2469 DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
2470 DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
2471 DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
2472 DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
2473 DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
2474 DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
2476 DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu),
2477 DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n),
2478 DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n),
2479 DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n),
2482 DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
2483 DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
2484 DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
2485 DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
2486 DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
2487 DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
2488 DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
2490 DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
2491 DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
2492 DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
2493 DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
2496 DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
2497 DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
2498 DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
2499 DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
2500 DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
2501 DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
2502 DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
2504 DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
2505 DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
2506 DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
2507 DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
2510 DEFINEREG2(PIPEEDPCONF, i830_debug_pipeconf),
2511 DEFINEREG2(HTOTAL_EDP, i830_debug_hvtotal),
2512 DEFINEREG2(HBLANK_EDP, i830_debug_hvsyncblank),
2513 DEFINEREG2(HSYNC_EDP, i830_debug_hvsyncblank),
2514 DEFINEREG2(VTOTAL_EDP, i830_debug_hvtotal),
2515 DEFINEREG2(VBLANK_EDP, i830_debug_hvsyncblank),
2516 DEFINEREG2(VSYNC_EDP, i830_debug_hvsyncblank),
2518 DEFINEREG2(PIPEEDP_DATA_M1, ironlake_debug_m_tu),
2519 DEFINEREG2(PIPEEDP_DATA_N1, ironlake_debug_n),
2520 DEFINEREG2(PIPEEDP_LINK_M1, ironlake_debug_n),
2521 DEFINEREG2(PIPEEDP_LINK_N1, ironlake_debug_n),
2524 DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
2525 DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
2526 DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
2528 DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
2529 DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
2530 DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
2532 DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting),
2533 DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
2534 DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
2538 DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
2539 DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
2540 DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
2541 DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
2542 DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
2543 DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
2546 DEFINEREG2(TRANSACONF, ironlake_debug_transconf),
2548 DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
2553 DEFINEREG2(BLC_PWM_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
2554 DEFINEREG2(BLC_PWM_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
2555 DEFINEREG2(BLC_PWM2_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
2556 DEFINEREG2(BLC_PWM2_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
2557 DEFINEREG2(BLC_MISC_CTL, hsw_debug_blc_misc_ctl),
2558 DEFINEREG2(BLC_PWM_PCH_CTL1, ibx_debug_blc_pwm_ctl1),
2559 DEFINEREG2(BLC_PWM_PCH_CTL2, ibx_debug_blc_pwm_ctl2),
2561 DEFINEREG2(UTIL_PIN_CTL, hsw_debug_util_pin_ctl),
2563 DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status),
2564 DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control),
2571 DEFINEREG2(SDEISR, hsw_debug_sinterrupt),
2605 DEFINEREG2(GEN6_RP_CONTROL, gen6_rp_control),