Lines Matching refs:__u64
144 __u64 bo_size;
146 __u64 alignment;
148 __u64 domains;
150 __u64 domain_flags;
181 __u64 bo_info_ptr;
257 __u64 flags;
282 __u64 flags;
318 __u64 addr;
319 __u64 size;
361 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
363 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
376 __u64 flags;
378 __u64 tiling_info;
392 __u64 addr_ptr;
406 __u64 timeout;
426 __u64 handle;
428 __u64 timeout;
437 __u64 status;
450 __u64 seq_no;
455 __u64 fences;
458 __u64 timeout_ns;
481 __u64 value;
525 __u64 va_address;
527 __u64 offset_in_bo;
529 __u64 map_size;
558 __u64 chunk_data;
569 __u64 chunks;
573 __u64 handle;
614 __u64 va_start;
630 __u64 handle;
645 __u64 point;
839 __u64 return_pointer;
903 __u64 vram_size;
904 __u64 vram_cpu_accessible_size;
905 __u64 gtt_size;
910 __u64 total_heap_size;
913 __u64 usable_heap_size;
921 __u64 heap_usage;
927 __u64 max_allocation;
966 __u64 max_engine_clock;
967 __u64 max_memory_clock;
978 __u64 ids_flags;
980 __u64 virtual_address_offset;
982 __u64 virtual_address_max;
999 __u64 prim_buf_gpu_addr;
1001 __u64 pos_buf_gpu_addr;
1003 __u64 cntl_sb_buf_gpu_addr;
1005 __u64 param_buf_gpu_addr;
1028 __u64 high_va_offset;
1030 __u64 high_va_max;
1034 __u64 tcc_disabled_mask;
1042 __u64 capabilities_flags;