Lines Matching refs:hw_info
117 struct radeon_hw_info hw_info; member
212 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
215 surf_man->hw_info.allow_2d = 1; in r6_init_hw_info()
221 surf_man->hw_info.num_pipes = 1; in r6_init_hw_info()
224 surf_man->hw_info.num_pipes = 2; in r6_init_hw_info()
227 surf_man->hw_info.num_pipes = 4; in r6_init_hw_info()
230 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info()
233 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info()
234 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
240 surf_man->hw_info.num_banks = 4; in r6_init_hw_info()
243 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
246 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
247 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
253 surf_man->hw_info.group_bytes = 256; in r6_init_hw_info()
256 surf_man->hw_info.group_bytes = 512; in r6_init_hw_info()
259 surf_man->hw_info.group_bytes = 256; in r6_init_hw_info()
260 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
275 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear()
280 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
309 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear_aligned()
311 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
337 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
345 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_1d()
371 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) / in r6_surface_init_2d()
373 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); in r6_surface_init_2d()
376 yalign = tilew * surf_man->hw_info.num_pipes; in r6_surface_init_2d()
382 MAX2(surf_man->hw_info.num_pipes * in r6_surface_init_2d()
383 surf_man->hw_info.num_banks * in r6_surface_init_2d()
434 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { in r6_surface_init()
497 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
500 surf_man->hw_info.allow_2d = 1; in eg_init_hw_info()
506 surf_man->hw_info.num_pipes = 1; in eg_init_hw_info()
509 surf_man->hw_info.num_pipes = 2; in eg_init_hw_info()
512 surf_man->hw_info.num_pipes = 4; in eg_init_hw_info()
515 surf_man->hw_info.num_pipes = 8; in eg_init_hw_info()
518 surf_man->hw_info.num_pipes = 8; in eg_init_hw_info()
519 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
525 surf_man->hw_info.num_banks = 4; in eg_init_hw_info()
528 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
531 surf_man->hw_info.num_banks = 16; in eg_init_hw_info()
534 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
535 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
541 surf_man->hw_info.group_bytes = 256; in eg_init_hw_info()
544 surf_man->hw_info.group_bytes = 512; in eg_init_hw_info()
547 surf_man->hw_info.group_bytes = 256; in eg_init_hw_info()
548 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
554 surf_man->hw_info.row_size = 1024; in eg_init_hw_info()
557 surf_man->hw_info.row_size = 2048; in eg_init_hw_info()
560 surf_man->hw_info.row_size = 4096; in eg_init_hw_info()
563 surf_man->hw_info.row_size = 4096; in eg_init_hw_info()
564 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
622 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples); in eg_surface_init_1d()
631 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); in eg_surface_init_1d()
675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
676 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea; in eg_surface_init_2d()
722 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { in eg_surface_sanity()
756 if (surf_man->hw_info.num_banks < surf->mtilea) { in eg_surface_sanity()
780 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { in eg_surface_sanity()
921 surf->mtilea = surf_man->hw_info.num_banks; in eg_surface_best()
924 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
974 surf->tile_split = surf_man->hw_info.row_size; in eg_surface_best()
975 surf->stencil_tile_split = surf_man->hw_info.row_size / 2; in eg_surface_best()
1013 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
1018 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) / in eg_surface_best()
1019 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16; in eg_surface_best()
1211 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1214 …if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_ar… in si_init_hw_info()
1215 surf_man->hw_info.allow_2d = 1; in si_init_hw_info()
1222 surf_man->hw_info.num_pipes = 1; in si_init_hw_info()
1225 surf_man->hw_info.num_pipes = 2; in si_init_hw_info()
1228 surf_man->hw_info.num_pipes = 4; in si_init_hw_info()
1231 surf_man->hw_info.num_pipes = 8; in si_init_hw_info()
1234 surf_man->hw_info.num_pipes = 8; in si_init_hw_info()
1235 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1241 surf_man->hw_info.num_banks = 4; in si_init_hw_info()
1244 surf_man->hw_info.num_banks = 8; in si_init_hw_info()
1247 surf_man->hw_info.num_banks = 16; in si_init_hw_info()
1250 surf_man->hw_info.num_banks = 8; in si_init_hw_info()
1251 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1257 surf_man->hw_info.group_bytes = 256; in si_init_hw_info()
1260 surf_man->hw_info.group_bytes = 512; in si_init_hw_info()
1263 surf_man->hw_info.group_bytes = 256; in si_init_hw_info()
1264 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1270 surf_man->hw_info.row_size = 1024; in si_init_hw_info()
1273 surf_man->hw_info.row_size = 2048; in si_init_hw_info()
1276 surf_man->hw_info.row_size = 4096; in si_init_hw_info()
1279 surf_man->hw_info.row_size = 4096; in si_init_hw_info()
1280 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1304 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in si_surface_sanity()
1347 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode]; in si_surface_sanity()
1398 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode]; in si_surface_sanity()
1527 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1532 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1557 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_1d()
1564 slice_align = surf_man->hw_info.group_bytes; in si_surface_init_1d()
1710 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in si_surface_init_2d_miptrees()
1867 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in cik_get_2d_params()
1945 tile_split = MIN2(surf_man->hw_info.row_size, tile_split); in cik_get_2d_params()
1953 gb_macrotile_mode = surf_man->hw_info.macrotile_mode_array[macrotile_index]; in cik_get_2d_params()
2040 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2043 …if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_ar… in cik_init_hw_info()
2044 …!radeon_get_value(surf_man->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, surf_man->hw_info.macrotile_… in cik_init_hw_info()
2045 surf_man->hw_info.allow_2d = 1; in cik_init_hw_info()
2052 surf_man->hw_info.num_pipes = 1; in cik_init_hw_info()
2055 surf_man->hw_info.num_pipes = 2; in cik_init_hw_info()
2058 surf_man->hw_info.num_pipes = 4; in cik_init_hw_info()
2061 surf_man->hw_info.num_pipes = 8; in cik_init_hw_info()
2064 surf_man->hw_info.num_pipes = 8; in cik_init_hw_info()
2065 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2071 surf_man->hw_info.num_banks = 4; in cik_init_hw_info()
2074 surf_man->hw_info.num_banks = 8; in cik_init_hw_info()
2077 surf_man->hw_info.num_banks = 16; in cik_init_hw_info()
2080 surf_man->hw_info.num_banks = 8; in cik_init_hw_info()
2081 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2087 surf_man->hw_info.group_bytes = 256; in cik_init_hw_info()
2090 surf_man->hw_info.group_bytes = 512; in cik_init_hw_info()
2093 surf_man->hw_info.group_bytes = 256; in cik_init_hw_info()
2094 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2100 surf_man->hw_info.row_size = 1024; in cik_init_hw_info()
2103 surf_man->hw_info.row_size = 2048; in cik_init_hw_info()
2106 surf_man->hw_info.row_size = 4096; in cik_init_hw_info()
2109 surf_man->hw_info.row_size = 4096; in cik_init_hw_info()
2110 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2132 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in cik_surface_sanity()
2234 tile_split = MIN2(surf_man->hw_info.row_size, tile_split); in cik_surface_init_2d()