Lines Matching refs:surf_man
95 typedef int (*hw_init_surface_t)(struct radeon_surface_manager *surf_man,
97 typedef int (*hw_best_surface_t)(struct radeon_surface_manager *surf_man,
137 static int radeon_get_family(struct radeon_surface_manager *surf_man) in radeon_get_family() argument
139 switch (surf_man->device_id) { in radeon_get_family()
140 #define CHIPSET(pci_id, name, fam) case pci_id: surf_man->family = CHIP_##fam; break; in radeon_get_family()
200 static int r6_init_hw_info(struct radeon_surface_manager *surf_man) in r6_init_hw_info() argument
206 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in r6_init_hw_info()
212 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
213 version = drmGetVersion(surf_man->fd); in r6_init_hw_info()
215 surf_man->hw_info.allow_2d = 1; in r6_init_hw_info()
221 surf_man->hw_info.num_pipes = 1; in r6_init_hw_info()
224 surf_man->hw_info.num_pipes = 2; in r6_init_hw_info()
227 surf_man->hw_info.num_pipes = 4; in r6_init_hw_info()
230 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info()
233 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info()
234 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
240 surf_man->hw_info.num_banks = 4; in r6_init_hw_info()
243 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
246 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
247 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
253 surf_man->hw_info.group_bytes = 256; in r6_init_hw_info()
256 surf_man->hw_info.group_bytes = 512; in r6_init_hw_info()
259 surf_man->hw_info.group_bytes = 256; in r6_init_hw_info()
260 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
266 static int r6_surface_init_linear(struct radeon_surface_manager *surf_man, in r6_surface_init_linear() argument
275 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear()
280 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
300 static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, in r6_surface_init_linear_aligned() argument
309 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear_aligned()
311 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
328 static int r6_surface_init_1d(struct radeon_surface_manager *surf_man, in r6_surface_init_1d() argument
337 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
345 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_1d()
361 static int r6_surface_init_2d(struct radeon_surface_manager *surf_man, in r6_surface_init_2d() argument
371 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) / in r6_surface_init_2d()
373 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); in r6_surface_init_2d()
376 yalign = tilew * surf_man->hw_info.num_pipes; in r6_surface_init_2d()
382 MAX2(surf_man->hw_info.num_pipes * in r6_surface_init_2d()
383 surf_man->hw_info.num_banks * in r6_surface_init_2d()
393 return r6_surface_init_1d(surf_man, surf, offset, i); in r6_surface_init_2d()
404 static int r6_surface_init(struct radeon_surface_manager *surf_man, in r6_surface_init() argument
434 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { in r6_surface_init()
457 r = r6_surface_init_linear(surf_man, surf, 0, 0); in r6_surface_init()
460 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); in r6_surface_init()
463 r = r6_surface_init_1d(surf_man, surf, 0, 0); in r6_surface_init()
466 r = r6_surface_init_2d(surf_man, surf, 0, 0); in r6_surface_init()
474 static int r6_surface_best(struct radeon_surface_manager *surf_man, in r6_surface_best() argument
485 static int eg_init_hw_info(struct radeon_surface_manager *surf_man) in eg_init_hw_info() argument
491 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in eg_init_hw_info()
497 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
498 version = drmGetVersion(surf_man->fd); in eg_init_hw_info()
500 surf_man->hw_info.allow_2d = 1; in eg_init_hw_info()
506 surf_man->hw_info.num_pipes = 1; in eg_init_hw_info()
509 surf_man->hw_info.num_pipes = 2; in eg_init_hw_info()
512 surf_man->hw_info.num_pipes = 4; in eg_init_hw_info()
515 surf_man->hw_info.num_pipes = 8; in eg_init_hw_info()
518 surf_man->hw_info.num_pipes = 8; in eg_init_hw_info()
519 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
525 surf_man->hw_info.num_banks = 4; in eg_init_hw_info()
528 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
531 surf_man->hw_info.num_banks = 16; in eg_init_hw_info()
534 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
535 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
541 surf_man->hw_info.group_bytes = 256; in eg_init_hw_info()
544 surf_man->hw_info.group_bytes = 512; in eg_init_hw_info()
547 surf_man->hw_info.group_bytes = 256; in eg_init_hw_info()
548 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
554 surf_man->hw_info.row_size = 1024; in eg_init_hw_info()
557 surf_man->hw_info.row_size = 2048; in eg_init_hw_info()
560 surf_man->hw_info.row_size = 4096; in eg_init_hw_info()
563 surf_man->hw_info.row_size = 4096; in eg_init_hw_info()
564 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
611 static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, in eg_surface_init_1d() argument
622 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples); in eg_surface_init_1d()
631 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); in eg_surface_init_1d()
652 static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, in eg_surface_init_2d() argument
675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
676 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea; in eg_surface_init_2d()
694 return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i); in eg_surface_init_2d()
705 static int eg_surface_sanity(struct radeon_surface_manager *surf_man, in eg_surface_sanity() argument
722 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { in eg_surface_sanity()
756 if (surf_man->hw_info.num_banks < surf->mtilea) { in eg_surface_sanity()
780 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { in eg_surface_sanity()
788 static int eg_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man, in eg_surface_init_1d_miptrees() argument
798 r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0); in eg_surface_init_1d_miptrees()
803 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1, in eg_surface_init_1d_miptrees()
810 static int eg_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, in eg_surface_init_2d_miptrees() argument
820 r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe, in eg_surface_init_2d_miptrees()
826 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1, in eg_surface_init_2d_miptrees()
833 static int eg_surface_init(struct radeon_surface_manager *surf_man, in eg_surface_init() argument
862 r = eg_surface_sanity(surf_man, surf, mode); in eg_surface_init()
873 r = r6_surface_init_linear(surf_man, surf, 0, 0); in eg_surface_init()
876 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); in eg_surface_init()
879 r = eg_surface_init_1d_miptrees(surf_man, surf); in eg_surface_init()
882 r = eg_surface_init_2d_miptrees(surf_man, surf); in eg_surface_init()
908 static int eg_surface_best(struct radeon_surface_manager *surf_man, in eg_surface_best() argument
921 surf->mtilea = surf_man->hw_info.num_banks; in eg_surface_best()
924 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
932 r = eg_surface_sanity(surf_man, surf, mode); in eg_surface_best()
974 surf->tile_split = surf_man->hw_info.row_size; in eg_surface_best()
975 surf->stencil_tile_split = surf_man->hw_info.row_size / 2; in eg_surface_best()
1013 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
1018 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) / in eg_surface_best()
1019 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16; in eg_surface_best()
1199 static int si_init_hw_info(struct radeon_surface_manager *surf_man) in si_init_hw_info() argument
1205 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in si_init_hw_info()
1211 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1212 version = drmGetVersion(surf_man->fd); in si_init_hw_info()
1214 …if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_ar… in si_init_hw_info()
1215 surf_man->hw_info.allow_2d = 1; in si_init_hw_info()
1222 surf_man->hw_info.num_pipes = 1; in si_init_hw_info()
1225 surf_man->hw_info.num_pipes = 2; in si_init_hw_info()
1228 surf_man->hw_info.num_pipes = 4; in si_init_hw_info()
1231 surf_man->hw_info.num_pipes = 8; in si_init_hw_info()
1234 surf_man->hw_info.num_pipes = 8; in si_init_hw_info()
1235 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1241 surf_man->hw_info.num_banks = 4; in si_init_hw_info()
1244 surf_man->hw_info.num_banks = 8; in si_init_hw_info()
1247 surf_man->hw_info.num_banks = 16; in si_init_hw_info()
1250 surf_man->hw_info.num_banks = 8; in si_init_hw_info()
1251 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1257 surf_man->hw_info.group_bytes = 256; in si_init_hw_info()
1260 surf_man->hw_info.group_bytes = 512; in si_init_hw_info()
1263 surf_man->hw_info.group_bytes = 256; in si_init_hw_info()
1264 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1270 surf_man->hw_info.row_size = 1024; in si_init_hw_info()
1273 surf_man->hw_info.row_size = 2048; in si_init_hw_info()
1276 surf_man->hw_info.row_size = 4096; in si_init_hw_info()
1279 surf_man->hw_info.row_size = 4096; in si_init_hw_info()
1280 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1286 static int si_surface_sanity(struct radeon_surface_manager *surf_man, in si_surface_sanity() argument
1304 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in si_surface_sanity()
1347 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode]; in si_surface_sanity()
1398 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode]; in si_surface_sanity()
1517 static int si_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, in si_surface_init_linear_aligned() argument
1527 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1532 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1550 static int si_surface_init_1d(struct radeon_surface_manager *surf_man, in si_surface_init_1d() argument
1557 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_1d()
1564 slice_align = surf_man->hw_info.group_bytes; in si_surface_init_1d()
1599 static int si_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man, in si_surface_init_1d_miptrees() argument
1605 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0); in si_surface_init_1d_miptrees()
1611 …r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0… in si_surface_init_1d_miptrees()
1617 static int si_surface_init_2d(struct radeon_surface_manager *surf_man, in si_surface_init_2d() argument
1681 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); in si_surface_init_2d()
1701 static int si_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, in si_surface_init_2d_miptrees() argument
1710 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in si_surface_init_2d_miptrees()
1713 …r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, su… in si_surface_init_2d_miptrees()
1719 …r = si_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, num_pipes, num_b… in si_surface_init_2d_miptrees()
1725 static int si_surface_init(struct radeon_surface_manager *surf_man, in si_surface_init() argument
1754 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in si_surface_init()
1765 r = r6_surface_init_linear(surf_man, surf, 0, 0); in si_surface_init()
1768 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); in si_surface_init()
1771 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in si_surface_init()
1774 r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in si_surface_init()
1785 static int si_surface_best(struct radeon_surface_manager *surf_man, in si_surface_best() argument
1800 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in si_surface_best()
1857 static void cik_get_2d_params(struct radeon_surface_manager *surf_man, in cik_get_2d_params() argument
1867 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in cik_get_2d_params()
1945 tile_split = MIN2(surf_man->hw_info.row_size, tile_split); in cik_get_2d_params()
1953 gb_macrotile_mode = surf_man->hw_info.macrotile_mode_array[macrotile_index]; in cik_get_2d_params()
2028 static int cik_init_hw_info(struct radeon_surface_manager *surf_man) in cik_init_hw_info() argument
2034 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in cik_init_hw_info()
2040 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2041 version = drmGetVersion(surf_man->fd); in cik_init_hw_info()
2043 …if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_ar… in cik_init_hw_info()
2044 …!radeon_get_value(surf_man->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, surf_man->hw_info.macrotile_… in cik_init_hw_info()
2045 surf_man->hw_info.allow_2d = 1; in cik_init_hw_info()
2052 surf_man->hw_info.num_pipes = 1; in cik_init_hw_info()
2055 surf_man->hw_info.num_pipes = 2; in cik_init_hw_info()
2058 surf_man->hw_info.num_pipes = 4; in cik_init_hw_info()
2061 surf_man->hw_info.num_pipes = 8; in cik_init_hw_info()
2064 surf_man->hw_info.num_pipes = 8; in cik_init_hw_info()
2065 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2071 surf_man->hw_info.num_banks = 4; in cik_init_hw_info()
2074 surf_man->hw_info.num_banks = 8; in cik_init_hw_info()
2077 surf_man->hw_info.num_banks = 16; in cik_init_hw_info()
2080 surf_man->hw_info.num_banks = 8; in cik_init_hw_info()
2081 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2087 surf_man->hw_info.group_bytes = 256; in cik_init_hw_info()
2090 surf_man->hw_info.group_bytes = 512; in cik_init_hw_info()
2093 surf_man->hw_info.group_bytes = 256; in cik_init_hw_info()
2094 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2100 surf_man->hw_info.row_size = 1024; in cik_init_hw_info()
2103 surf_man->hw_info.row_size = 2048; in cik_init_hw_info()
2106 surf_man->hw_info.row_size = 4096; in cik_init_hw_info()
2109 surf_man->hw_info.row_size = 4096; in cik_init_hw_info()
2110 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2116 static int cik_surface_sanity(struct radeon_surface_manager *surf_man, in cik_surface_sanity() argument
2132 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in cik_surface_sanity()
2176 cik_get_2d_params(surf_man, 1, surf->nsamples, false, in cik_surface_sanity()
2188 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, in cik_surface_sanity()
2214 static int cik_surface_init_2d(struct radeon_surface_manager *surf_man, in cik_surface_init_2d() argument
2234 tile_split = MIN2(surf_man->hw_info.row_size, tile_split); in cik_surface_init_2d()
2283 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); in cik_surface_init_2d()
2303 static int cik_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, in cik_surface_init_2d_miptrees() argument
2310 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, in cik_surface_init_2d_miptrees()
2314 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, in cik_surface_init_2d_miptrees()
2321 r = cik_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, in cik_surface_init_2d_miptrees()
2329 static int cik_surface_init(struct radeon_surface_manager *surf_man, in cik_surface_init() argument
2358 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in cik_surface_init()
2369 r = r6_surface_init_linear(surf_man, surf, 0, 0); in cik_surface_init()
2372 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); in cik_surface_init()
2375 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in cik_surface_init()
2378 r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in cik_surface_init()
2389 static int cik_surface_best(struct radeon_surface_manager *surf_man, in cik_surface_best() argument
2404 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in cik_surface_best()
2414 struct radeon_surface_manager *surf_man; in radeon_surface_manager_new() local
2416 surf_man = calloc(1, sizeof(struct radeon_surface_manager)); in radeon_surface_manager_new()
2417 if (surf_man == NULL) { in radeon_surface_manager_new()
2420 surf_man->fd = fd; in radeon_surface_manager_new()
2421 if (radeon_get_value(fd, RADEON_INFO_DEVICE_ID, &surf_man->device_id)) { in radeon_surface_manager_new()
2424 if (radeon_get_family(surf_man)) { in radeon_surface_manager_new()
2428 if (surf_man->family <= CHIP_RV740) { in radeon_surface_manager_new()
2429 if (r6_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2432 surf_man->surface_init = &r6_surface_init; in radeon_surface_manager_new()
2433 surf_man->surface_best = &r6_surface_best; in radeon_surface_manager_new()
2434 } else if (surf_man->family <= CHIP_ARUBA) { in radeon_surface_manager_new()
2435 if (eg_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2438 surf_man->surface_init = &eg_surface_init; in radeon_surface_manager_new()
2439 surf_man->surface_best = &eg_surface_best; in radeon_surface_manager_new()
2440 } else if (surf_man->family < CHIP_BONAIRE) { in radeon_surface_manager_new()
2441 if (si_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2444 surf_man->surface_init = &si_surface_init; in radeon_surface_manager_new()
2445 surf_man->surface_best = &si_surface_best; in radeon_surface_manager_new()
2447 if (cik_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2450 surf_man->surface_init = &cik_surface_init; in radeon_surface_manager_new()
2451 surf_man->surface_best = &cik_surface_best; in radeon_surface_manager_new()
2454 return surf_man; in radeon_surface_manager_new()
2456 free(surf_man); in radeon_surface_manager_new()
2461 radeon_surface_manager_free(struct radeon_surface_manager *surf_man) in radeon_surface_manager_free() argument
2463 free(surf_man); in radeon_surface_manager_free()
2466 static int radeon_surface_sanity(struct radeon_surface_manager *surf_man, in radeon_surface_sanity() argument
2471 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) { in radeon_surface_sanity()
2514 if (surf_man->family >= CHIP_RV770) { in radeon_surface_sanity()
2535 radeon_surface_init(struct radeon_surface_manager *surf_man, in radeon_surface_init() argument
2544 r = radeon_surface_sanity(surf_man, surf, type, mode); in radeon_surface_init()
2548 return surf_man->surface_init(surf_man, surf); in radeon_surface_init()
2552 radeon_surface_best(struct radeon_surface_manager *surf_man, in radeon_surface_best() argument
2561 r = radeon_surface_sanity(surf_man, surf, type, mode); in radeon_surface_best()
2565 return surf_man->surface_best(surf_man, surf); in radeon_surface_best()