168                         struct radeon_surface_level *surflevel,  in surf_minify()  argument
173     surflevel->npix_x = mip_minify(surf->npix_x, level);  in surf_minify()
174     surflevel->npix_y = mip_minify(surf->npix_y, level);  in surf_minify()
175     surflevel->npix_z = mip_minify(surf->npix_z, level);  in surf_minify()
176     surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;  in surf_minify()
177     surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;  in surf_minify()
178     surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;  in surf_minify()
179     if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&  in surf_minify()
181         if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) {  in surf_minify()
182             surflevel->mode = RADEON_SURF_MODE_1D;  in surf_minify()
186     surflevel->nblk_x  = ALIGN(surflevel->nblk_x, xalign);  in surf_minify()
187     surflevel->nblk_y  = ALIGN(surflevel->nblk_y, yalign);  in surf_minify()
188     surflevel->nblk_z  = ALIGN(surflevel->nblk_z, zalign);  in surf_minify()
190     surflevel->offset = offset;  in surf_minify()
191     surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;  in surf_minify()
192     surflevel->slice_size = (uint64_t)surflevel->pitch_bytes * surflevel->nblk_y;  in surf_minify()
194     surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;  in surf_minify()
571                            struct radeon_surface_level *surflevel,  in eg_surf_minify()  argument
582     surflevel->npix_x = mip_minify(surf->npix_x, level);  in eg_surf_minify()
583     surflevel->npix_y = mip_minify(surf->npix_y, level);  in eg_surf_minify()
584     surflevel->npix_z = mip_minify(surf->npix_z, level);  in eg_surf_minify()
585     surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;  in eg_surf_minify()
586     surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;  in eg_surf_minify()
587     surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;  in eg_surf_minify()
588     if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&  in eg_surf_minify()
590         if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) {  in eg_surf_minify()
591             surflevel->mode = RADEON_SURF_MODE_1D;  in eg_surf_minify()
595     surflevel->nblk_x  = ALIGN(surflevel->nblk_x, mtilew);  in eg_surf_minify()
596     surflevel->nblk_y  = ALIGN(surflevel->nblk_y, mtileh);  in eg_surf_minify()
597     surflevel->nblk_z  = ALIGN(surflevel->nblk_z, 1);  in eg_surf_minify()
600     mtile_pr = surflevel->nblk_x / mtilew;  in eg_surf_minify()
602     mtile_ps = (mtile_pr * surflevel->nblk_y) / mtileh;  in eg_surf_minify()
604     surflevel->offset = offset;  in eg_surf_minify()
605     surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;  in eg_surf_minify()
606     surflevel->slice_size = (uint64_t)mtile_ps * mtileb * slice_pt;  in eg_surf_minify()
608     surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;  in eg_surf_minify()
1422                            struct radeon_surface_level *surflevel,  in si_surf_minify()  argument
1428         surflevel->npix_x = surf->npix_x;  in si_surf_minify()
1430         surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);  in si_surf_minify()
1432     surflevel->npix_y = mip_minify(surf->npix_y, level);  in si_surf_minify()
1433     surflevel->npix_z = mip_minify(surf->npix_z, level);  in si_surf_minify()
1436         surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w;  in si_surf_minify()
1437         surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h;  in si_surf_minify()
1438         surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d;  in si_surf_minify()
1440         surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;  in si_surf_minify()
1441         surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;  in si_surf_minify()
1442         surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;  in si_surf_minify()
1445     surflevel->nblk_y  = ALIGN(surflevel->nblk_y, yalign);  in si_surf_minify()
1454     else if (surflevel->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)  in si_surf_minify()
1456         xalign = MAX2(xalign, slice_align / bpe / surflevel->nblk_y);  in si_surf_minify()
1458     surflevel->nblk_x  = ALIGN(surflevel->nblk_x, xalign);  in si_surf_minify()
1459     surflevel->nblk_z  = ALIGN(surflevel->nblk_z, zalign);  in si_surf_minify()
1461     surflevel->offset = offset;  in si_surf_minify()
1462     surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;  in si_surf_minify()
1463     surflevel->slice_size = ALIGN((uint64_t)surflevel->pitch_bytes * surflevel->nblk_y,  in si_surf_minify()
1466     surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;  in si_surf_minify()
1470                               struct radeon_surface_level *surflevel,  in si_surf_minify_2d()  argument
1478         surflevel->npix_x = surf->npix_x;  in si_surf_minify_2d()
1480         surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);  in si_surf_minify_2d()
1482     surflevel->npix_y = mip_minify(surf->npix_y, level);  in si_surf_minify_2d()
1483     surflevel->npix_z = mip_minify(surf->npix_z, level);  in si_surf_minify_2d()
1486         surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w;  in si_surf_minify_2d()
1487         surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h;  in si_surf_minify_2d()
1488         surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d;  in si_surf_minify_2d()
1490         surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;  in si_surf_minify_2d()
1491         surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;  in si_surf_minify_2d()
1492         surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;  in si_surf_minify_2d()
1495     if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&  in si_surf_minify_2d()
1497         if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) {  in si_surf_minify_2d()
1498             surflevel->mode = RADEON_SURF_MODE_1D;  in si_surf_minify_2d()
1502     surflevel->nblk_x  = ALIGN(surflevel->nblk_x, xalign);  in si_surf_minify_2d()
1503     surflevel->nblk_y  = ALIGN(surflevel->nblk_y, yalign);  in si_surf_minify_2d()
1504     surflevel->nblk_z  = ALIGN(surflevel->nblk_z, zalign);  in si_surf_minify_2d()
1507     mtile_pr = surflevel->nblk_x / xalign;  in si_surf_minify_2d()
1509     mtile_ps = (mtile_pr * surflevel->nblk_y) / yalign;  in si_surf_minify_2d()
1510     surflevel->offset = offset;  in si_surf_minify_2d()
1511     surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;  in si_surf_minify_2d()
1512     surflevel->slice_size = (uint64_t)mtile_ps * mtileb * slice_pt;  in si_surf_minify_2d()
1514     surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;  in si_surf_minify_2d()