arm-v8.1a-neon-intrinsics.c - OpenGrok cross reference for /external/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c

Lines Matching +full:llvm +full:- +full:3
1 // RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon \
2 // RUN:  -S -emit-llvm -o - %s \
3 // RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM
5 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
6 // RUN:  -target-feature +v8.1a -S -emit-llvm -o - %s \
7 // RUN:  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
9 // REQUIRES: arm-registered-target,aarch64-registered-target
13 // CHECK-LABEL: test_vqrdmlah_s16
15 // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})  in test_vqrdmlah_s16()
16 // CHECK-ARM: call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})  in test_vqrdmlah_s16()
18 // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%…  in test_vqrdmlah_s16()
19 // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}…  in test_vqrdmlah_s16()
23 // CHECK-LABEL: test_vqrdmlah_s32
25 // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})  in test_vqrdmlah_s32()
26 // CHECK-ARM: call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})  in test_vqrdmlah_s32()
28 // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%…  in test_vqrdmlah_s32()
29 // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}…  in test_vqrdmlah_s32()
33 // CHECK-LABEL: test_vqrdmlahq_s16
35 // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})  in test_vqrdmlahq_s16()
36 // CHECK-ARM: call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})  in test_vqrdmlahq_s16()
38 // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%…  in test_vqrdmlahq_s16()
39 // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}…  in test_vqrdmlahq_s16()
43 // CHECK-LABEL: test_vqrdmlahq_s32
45 // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})  in test_vqrdmlahq_s32()
46 // CHECK-ARM: call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})  in test_vqrdmlahq_s32()
48 // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%…  in test_vqrdmlahq_s32()
49 // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}…  in test_vqrdmlahq_s32()
53 // CHECK-LABEL: test_vqrdmlah_lane_s16
55 // CHECK-ARM: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <4 x i32> <i32 3, i32 3, i32 3, i…  in test_vqrdmlah_lane_s16()
56 // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})  in test_vqrdmlah_lane_s16()
57 // CHECK-ARM: call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})  in test_vqrdmlah_lane_s16()
59 // CHECK-AARCH64: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <4 x i32> <i32 3, i32 3, i32 …  in test_vqrdmlah_lane_s16()
60 // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%…  in test_vqrdmlah_lane_s16()
61 // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}…  in test_vqrdmlah_lane_s16()
62   return vqrdmlah_lane_s16(a, b, c, 3);  in test_vqrdmlah_lane_s16()
65 // CHECK-LABEL: test_vqrdmlah_lane_s32
67 // CHECK-ARM: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <2 x i32> <i32 1, i32 1>  in test_vqrdmlah_lane_s32()
68 // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})  in test_vqrdmlah_lane_s32()
69 // CHECK-ARM: call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})  in test_vqrdmlah_lane_s32()
71 // CHECK-AARCH64: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <2 x i32> <i32 1, i32 1>  in test_vqrdmlah_lane_s32()
72 // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%…  in test_vqrdmlah_lane_s32()
73 // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}…  in test_vqrdmlah_lane_s32()
77 // CHECK-LABEL: test_vqrdmlahq_lane_s16
79 // CHECK-ARM: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <8 x i32> <i32 3, i32 3, i32 3, i…  in test_vqrdmlahq_lane_s16()
80 // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})  in test_vqrdmlahq_lane_s16()
81 // CHECK-ARM: call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})  in test_vqrdmlahq_lane_s16()
83 // CHECK-AARCH64: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <8 x i32> <i32 3, i32 3, i32 …  in test_vqrdmlahq_lane_s16()
84 // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%…  in test_vqrdmlahq_lane_s16()
85 // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}…  in test_vqrdmlahq_lane_s16()
86   return vqrdmlahq_lane_s16(a, b, c, 3);  in test_vqrdmlahq_lane_s16()
89 // CHECK-LABEL: test_vqrdmlahq_lane_s32
91 // CHECK-ARM: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 1, i…  in test_vqrdmlahq_lane_s32()
92 // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})  in test_vqrdmlahq_lane_s32()
93 // CHECK-ARM: call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})  in test_vqrdmlahq_lane_s32()
95 // CHECK-AARCH64: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 …  in test_vqrdmlahq_lane_s32()
96 // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%…  in test_vqrdmlahq_lane_s32()
97 // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}…  in test_vqrdmlahq_lane_s32()
101 // CHECK-LABEL: test_vqrdmlsh_s16
103 // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})  in test_vqrdmlsh_s16()
104 // CHECK-ARM: call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})  in test_vqrdmlsh_s16()
106 // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%…  in test_vqrdmlsh_s16()
107 // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}…  in test_vqrdmlsh_s16()
111 // CHECK-LABEL: test_vqrdmlsh_s32
113 // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})  in test_vqrdmlsh_s32()
114 // CHECK-ARM: call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})  in test_vqrdmlsh_s32()
116 // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%…  in test_vqrdmlsh_s32()
117 // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}…  in test_vqrdmlsh_s32()
121 // CHECK-LABEL: test_vqrdmlshq_s16
123 // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})  in test_vqrdmlshq_s16()
124 // CHECK-ARM: call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})  in test_vqrdmlshq_s16()
126 // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%…  in test_vqrdmlshq_s16()
127 // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}…  in test_vqrdmlshq_s16()
131 // CHECK-LABEL: test_vqrdmlshq_s32
133 // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})  in test_vqrdmlshq_s32()
134 // CHECK-ARM: call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})  in test_vqrdmlshq_s32()
136 // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%…  in test_vqrdmlshq_s32()
137 // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}…  in test_vqrdmlshq_s32()
141 // CHECK-LABEL: test_vqrdmlsh_lane_s16
143 // CHECK-ARM: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <4 x i32> <i32 3, i32 3, i32 3, i…  in test_vqrdmlsh_lane_s16()
144 // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})  in test_vqrdmlsh_lane_s16()
145 // CHECK-ARM: call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})  in test_vqrdmlsh_lane_s16()
147 // CHECK-AARCH64: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <4 x i32> <i32 3, i32 3, i32 …  in test_vqrdmlsh_lane_s16()
148 // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%…  in test_vqrdmlsh_lane_s16()
149 // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}…  in test_vqrdmlsh_lane_s16()
150   return vqrdmlsh_lane_s16(a, b, c, 3);  in test_vqrdmlsh_lane_s16()
153 // CHECK-LABEL: test_vqrdmlsh_lane_s32
155 // CHECK-ARM: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <2 x i32> <i32 1, i32 1>  in test_vqrdmlsh_lane_s32()
156 // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})  in test_vqrdmlsh_lane_s32()
157 // CHECK-ARM: call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})  in test_vqrdmlsh_lane_s32()
159 // CHECK-AARCH64: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <2 x i32> <i32 1, i32 1>  in test_vqrdmlsh_lane_s32()
160 // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%…  in test_vqrdmlsh_lane_s32()
161 // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}…  in test_vqrdmlsh_lane_s32()
165 // CHECK-LABEL: test_vqrdmlshq_lane_s16
167 // CHECK-ARM: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <8 x i32> <i32 3, i32 3, i32 3, i…  in test_vqrdmlshq_lane_s16()
168 // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})  in test_vqrdmlshq_lane_s16()
169 // CHECK-ARM: call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})  in test_vqrdmlshq_lane_s16()
171 // CHECK-AARCH64: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <8 x i32> <i32 3, i32 3, i32 …  in test_vqrdmlshq_lane_s16()
172 // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%…  in test_vqrdmlshq_lane_s16()
173 // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}…  in test_vqrdmlshq_lane_s16()
174   return vqrdmlshq_lane_s16(a, b, c, 3);  in test_vqrdmlshq_lane_s16()
177 // CHECK-LABEL: test_vqrdmlshq_lane_s32
179 // CHECK-ARM: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 1, i…  in test_vqrdmlshq_lane_s32()
180 // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})  in test_vqrdmlshq_lane_s32()
181 // CHECK-ARM: call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})  in test_vqrdmlshq_lane_s32()
183 // CHECK-AARCH64: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 …  in test_vqrdmlshq_lane_s32()
184 // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%…  in test_vqrdmlshq_lane_s32()
185 // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}…  in test_vqrdmlshq_lane_s32()