Lines Matching +refs:llvm +refs:mode +refs:syntax +refs:table
31 ``llvm/lib/Target/AMDGPU`` directory.
44 .. table:: AMDGPU Architectures
45 :name: amdgpu-architecture-table
54 .. table:: AMDGPU Vendors
55 :name: amdgpu-vendor-table
64 .. table:: AMDGPU Operating Systems
85 .. table:: AMDGPU Environments
86 :name: amdgpu-environment-table
104 .. table:: AMDGPU Processors
105 :name: amdgpu-processor-table
424 :ref:`amdgpu-processor-table`.
454 .. table:: AMDGPU Target Features
455 :name: amdgpu-target-features-table
461 cumode - ``-m[no-]cumode`` Control the wavefront execution mode used
463 native WGP wavefront execution mode is used,
464 when enabled CU wavefront execution mode is used
506 <https://clang.llvm.org/docs/ClangOffloadBundler.html>`_ for a general
511 :ref:`amdgpu-processor-table`. The non-canonical form target ID allows both
516 Is a target feature name specified in :ref:`amdgpu-target-features-table` that
518 is specified in :ref:`amdgpu-processor-table`. Those that can be specifeid in
532 <https://clang.llvm.org/docs/ClangOffloadBundler.html>`_.
546 :ref:`amdgpu-address-spaces-table`. Only 64-bit process address spaces are
549 .. table:: AMDGPU Address Spaces
550 :name: amdgpu-address-spaces-table
570 of :ref:`amdgpu-processor-table` specifies *Does not support generic address
592 In 64-bit address mode the aperture sizes are 2^32 bytes and the base is
687 table :ref:`amdgpu-amdhsa-llvm-sync-scopes-table`).
693 .. table:: AMDHSA LLVM Sync Scopes
694 :name: amdgpu-amdhsa-llvm-sync-scopes-table
787 .. table:: AMDGPU LLVM IR Attributes
788 :name: amdgpu-llvm-ir-attributes-table
799 … :ref:`opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table`).
808 … mode register to be set on entry. Overrides the default for
811 … the mode register to be set on entry. Overrides the default
831 .. table:: AMDGPU ELF Header
832 :name: amdgpu-elf-header-table
852 ``e_flags`` See :ref:`amdgpu-elf-header-e_flags-v2-table`,
853 :ref:`amdgpu-elf-header-e_flags-table-v3`,
854 and :ref:`amdgpu-elf-header-e_flags-table-v4`
859 .. table:: AMDGPU ELF Header Enumeration Values
860 :name: amdgpu-elf-header-enumeration-values-table
939 :ref:`amdgpu-processor-table`). The specific processor is specified in the
943 :ref:`amdgpu-elf-header-e_flags-table-v3` and
944 :ref:`amdgpu-elf-header-e_flags-table-v4`).
953 .. table:: AMDGPU ELF Header ``e_flags`` for Code Object V2
954 :name: amdgpu-elf-header-e_flags-v2-table
980 .. table:: AMDGPU ELF Header ``e_flags`` for Code Object V3
981 :name: amdgpu-elf-header-e_flags-table-v3
990 :ref:`amdgpu-ef-amdgpu-mach-table`.
1015 .. table:: AMDGPU ELF Header ``e_flags`` for Code Object V4
1016 :name: amdgpu-elf-header-e_flags-table-v4
1025 :ref:`amdgpu-ef-amdgpu-mach-table`.
1042 .. table:: AMDGPU ``EF_AMDGPU_MACH`` Values
1043 :name: amdgpu-ef-amdgpu-mach-table
1047 :ref:`amdgpu-processor-table`)
1104 .. table:: AMDGPU ELF Sections
1105 :name: amdgpu-elf-sections-table
1192 .. table:: AMDGPU Code Object V2 ELF Note Records
1193 :name: amdgpu-elf-note-records-v2-table
1209 .. table:: AMDGPU Code Object V2 ELF Note Record Enumeration Values
1210 :name: amdgpu-elf-note-record-enumeration-values-v2-table
1275 :ref:`amdgpu-elf-note-record-supported_processors-v2-table` for a list of
1276 processors and the corresponding target ID. In the table the note record ISA
1287 :ref:`amdgpu-elf-note-record-supported_processors-v2-table` but the ``xnack``
1299 See :ref:`amdgpu-elf-note-record-supported_processors-v2-table` for a mapping
1309 :ref:`amdgpu-amdhsa-code-object-metadata-v2` for the syntax of the code object
1312 .. table:: AMDGPU Code Object V2 Supported Processors and Fixed Target Feature Settings
1313 :name: amdgpu-elf-note-record-supported_processors-v2-table
1356 .. table:: AMDGPU Code Object V3 to V4 ELF Note Records
1357 :name: amdgpu-elf-note-records-table-v3-v4
1368 .. table:: AMDGPU Code Object V3 to V4 ELF Note Record Enumeration Values
1369 :name: amdgpu-elf-note-record-enumeration-values-table-v3-v4
1392 .. table:: AMDGPU ELF Symbols
1393 :name: amdgpu-elf-symbols-table
1459 Represents the offset into the global offset table at which the relocation
1463 Represents the address of the global offset table.
1481 .. table:: AMDGPU ELF Relocation Records
1482 :name: amdgpu-elf-relocation-records-table
1524 The loaded code object path URI syntax is defined by the following BNF syntax:
1601 rather than being dynamic according to the wavefront size mode. Similarly,
1606 that match the mode in which the code it is generating will be executed.
1610 :ref:`amdgpu-dwarf-register-mapping-table`. All AMDGPU targets use the same
1613 .. table:: AMDGPU DWARF Register Mapping
1614 :name: amdgpu-dwarf-register-mapping-table
1625 executing in wavefront 32 mode.
1634 executing in wavefront 64 mode.
1646 mode.
1649 executing in wavefront 32 mode.*
1652 mode.
1655 executing in wavefront 64 mode.*
1662 mode.
1665 executing in wavefront 32 mode.*
1668 mode.
1671 executing in wavefront 32 mode.*
1674 mode.
1677 executing in wavefront 64 mode.*
1680 mode.
1683 executing in wavefront 64 mode.*
1695 If the wavefront size is 32 lanes then the wavefront 32 mode register
1697 mode register definitions are used. Some AMDGPU targets support executing in
1698 both wavefront 32 and wavefront 64 mode. The register definitions corresponding
1699 to the wavefront mode of the generated code will be used.
1717 :ref:`amdgpu-dwarf-address-class-mapping-table`.
1719 .. table:: AMDGPU DWARF Address Class Mapping
1720 :name: amdgpu-dwarf-address-class-mapping-table
1759 :ref:`amdgpu-dwarf-address-space-mapping-table`.
1761 .. table:: AMDGPU DWARF Address Space Mapping
1762 :name: amdgpu-dwarf-address-space-mapping-table
1890 to the subprogram. See :ref:`amdgpu-dwarf-dw-at-llvm-lane-pc` for an example.
1900 .. _amdgpu-dwarf-dw-at-llvm-lane-pc:
2175 :ref:`amdgpu-dwarf-amdgpu-dw-at-llvm-active-lane` rather than the actual
2176 ``EXEC`` mask in order to support whole or quad wavefront mode.
2178 .. _amdgpu-dwarf-amdgpu-dw-at-llvm-active-lane:
2187 The execution mask may be modified to implement whole or quad wavefront mode
2244 Add to :ref:`amdgpu-processor-table` table.
2250 Add to :ref:`amdgpu-processor-table` table.
2277 For AMDGPU the lookup by name section header table:
2308 For AMDGPU the lookup by address section header table:
2333 in wavefront32 or wavefront64 mode? Or used to specify the architecture ISA?
2352 OpenCL language runtime) may be embedded into the DWARF Version 5 line table.
2355 <amdgpu-dwarf-line-number-information-dw-lnct-llvm-source>`.
2358 :ref:`amdgpu-clang-debug-options-table`.
2360 .. table:: AMDGPU Clang Debug Options
2361 :name: amdgpu-clang-debug-options-table
2459 defined in table :ref:`amdgpu-amdhsa-code-object-metadata-map-v2-table` and
2468 .. table:: AMDHSA Code Object V2 Metadata Map
2469 :name: amdgpu-amdhsa-code-object-metadata-map-v2-table
2506 … :ref:`amdgpu-amdhsa-code-object-kernel-metadata-map-v2-table`
2512 .. table:: AMDHSA Code Object V2 Kernel Metadata Map
2513 :name: amdgpu-amdhsa-code-object-kernel-metadata-map-v2-table
2535 … :ref:`amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-v2-table`
2539 … :ref:`amdgpu-amdhsa-code-object-kernel-argument-metadata-map-v2-table`
2543 … :ref:`amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-v2-table`
2549 .. table:: AMDHSA Code Object V2 Kernel Attribute Metadata Map
2550 :name: amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-v2-table
2590 .. table:: AMDHSA Code Object V2 Kernel Argument Metadata Map
2591 :name: amdgpu-amdhsa-code-object-kernel-argument-metadata-map-v2-table
2785 .. table:: AMDHSA Code Object V2 Kernel Code Properties Metadata Map
2786 :name: amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-v2-table
2878 keys defined in table
2879 :ref:`amdgpu-amdhsa-code-object-metadata-map-table-v3` and referenced
2889 .. table:: AMDHSA Code Object V3 Metadata Map
2890 :name: amdgpu-amdhsa-code-object-metadata-map-table-v3
2927 … :ref:`amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3`
2934 .. table:: AMDHSA Code Object V3 Kernel Metadata Map
2935 :name: amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3
2959 … :ref:`amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3`
3078 .. table:: AMDHSA Code Object V3 Kernel Argument Metadata Map
3079 :name: amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3
3279 defined in table :ref:`amdgpu-amdhsa-code-object-metadata-map-table-v3`.
3281 ….. table:: AMDHSA Code Object V4 Metadata Map Changes from :ref:`amdgpu-amdhsa-code-object-metadat…
3282 :name: amdgpu-amdhsa-code-object-metadata-map-table-v4
3291 "amdhsa.target" string Required The target name of the code using the syntax:
3321 the kernel mode driver to initialize and register the AQL queue with CP.
3376 .. table:: AMDHSA Memory Spaces
3377 :name: amdgpu-amdhsa-memory-spaces-table
3446 address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32
3493 :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
3495 .. table:: Code Object V3 Kernel Descriptor
3496 :name: amdgpu-amdhsa-kernel-descriptor-v3-table
3567 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-table`.
3574 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
3581 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
3606 wavefront size 64 mode.
3609 32 mode.
3621 .. table:: compute_pgm_rsrc1 for GFX6-GFX10
3622 :name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table
3660 :ref:`amdhsa-kernel-directives-table`).
3700 table.
3716 :ref:`amdhsa-kernel-directives-table`).
3727 mode for single (32
3733 mode values are defined in
3734 … :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
3740 denorm mode for half/double (16
3746 mode values are defined in
3747 … :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
3752 with specified denorm mode
3758 Floating point denorm mode
3760 … :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
3765 with specified denorm mode
3771 Floating point denorm mode
3773 … :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
3781 mode.
3787 with DX10 clamp mode
3800 in single step mode.
3806 with IEEE mode
3842 mode.
3860 CU wavefront execution mode.
3862 in WGP wavefront execution mode.
3907 .. table:: compute_pgm_rsrc2 for GFX6-GFX10
3908 :name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table
3969 … :ref:`amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table`
4060 .. table:: compute_pgm_rsrc3 for GFX10
4061 :name: amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-table
4075 .. table:: Floating Point Rounding Mode Enumeration Values
4076 :name: amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table
4089 .. table:: Floating Point Denorm Mode Enumeration Values
4090 :name: amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table
4104 .. table:: System VGPR Work-Item ID Enumeration Values
4105 :name: amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table
4143 :ref:`amdgpu-amdhsa-sgpr-register-set-up-order-table`.
4145 .. table:: SGPR Register Set Up Order
4146 :name: amdgpu-amdhsa-sgpr-register-set-up-order-table
4346 :ref:`amdgpu-amdhsa-vgpr-register-set-up-order-table`.
4348 .. table:: VGPR Register Set Up Order
4349 :name: amdgpu-amdhsa-vgpr-register-set-up-order-table
4575 space. The code sequences in the table indicate what can be omitted for the
4612 table
4613 :ref:`amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-table`.
4615 .. table:: AMDHSA Memory Model Single Thread Optimization Constraints
4616 :name: amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-table
4743 in table :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table`.
4745 .. table:: AMDHSA Memory Model Code Sequences GFX6-GFX9
4746 :name: amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table
5896 WGP. In CU wavefront execution mode the wavefronts may be executed by
5897 different SIMDs in the same CU. In WGP wavefront execution mode the
5991 Wavefronts are executed in native mode with in-order reporting of loads and
5992 sample instructions. In this mode vmcnt reports completion of load, atomic with
5995 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
5997 Wavefronts can be executed in WGP or CU wavefront execution mode:
5999 * In WGP wavefront execution mode the wavefronts of a work-group are executed
6004 * In CU wavefront execution mode the wavefronts of a work-group are executed on
6011 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table` and
6015 table :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx10-table`.
6017 .. table:: AMDHSA Memory Model Code Sequences GFX10
6018 :name: amdgpu-amdhsa-memory-model-code-sequences-gfx10-table
6065 mode, omit glc=1.
6096 mode, omit glc=1.
6101 mode, omit.
6113 mode, omit.
6139 mode, omit.
6149 mode, omit glc=1.
6155 mode, omit vmcnt(0).
6175 mode, omit.
6240 mode, omit.
6255 mode, omit.
6288 mode, omit vm/vscnt(0).
6306 mode, omit.
6377 mode, omit vmcnt(0) and
6467 mode, omit.
6576 mode, omit vmcnt(0) and
6624 mode, omit.
6713 mode, omit vmcnt(0) and
6760 mode, omit.
6845 mode, omit vmcnt(0) and
6998 mode, omit vmcnt(0) and
7052 mode, omit.
7069 mode, omit.
7078 mode, omit.
7128 mode, omit.
7139 mode, omit vmcnt(0) and
7187 mode, omit vmcnt(0) and
7203 mode, omit.
7362 mode, omit vmcnt(0) and
7477 mode, omit.
7599 mode, omit vmcnt(0) and
7710 mode, omit.
7930 - :ref:`amdgpu-trap-handler-for-amdhsa-os-v2-table`
7931 - :ref:`amdgpu-trap-handler-for-amdhsa-os-v3-table`
7932 - :ref:`amdgpu-trap-handler-for-amdhsa-os-v4-table`
7934 .. table:: AMDGPU Trap Handler for AMDHSA OS Code Object V2
7935 :name: amdgpu-trap-handler-for-amdhsa-os-v2-table
7946 ``llvm.trap`` ``s_trap 0x02`` ``SGPR0-1``: Causes wave to be halted with the PC at
7953 ``llvm.debugtrap`` ``s_trap 0x03`` *none* - If debugger not enabled then behaves
7974 .. table:: AMDGPU Trap Handler for AMDHSA OS Code Object V3
7975 :name: amdgpu-trap-handler-for-amdhsa-os-v3-table
7988 ``llvm.trap`` ``s_trap 0x02`` ``SGPR0-1``: Causes wave to be halted with the PC at
7995 ``llvm.debugtrap`` ``s_trap 0x03`` *none* - If debugger not enabled then behaves
8016 .. table:: AMDGPU Trap Handler for AMDHSA OS Code Object V4
8017 :name: amdgpu-trap-handler-for-amdhsa-os-v4-table
8029 …``llvm.trap`` ``s_trap 0x02`` ``SGPR0-1``: *none* Causes wave to be halted with t…
8036 …``llvm.debugtrap`` ``s_trap 0x03`` *none* *none* - If debugger not enabled then …
8291 .. table:: Work-item implicit argument layout
8292 :name: amdgpu-amdhsa-workitem-implicit-argument-layout-table
8306 :ref:`amdgpu-amdhsa-sgpr-register-set-up-order-table`.
8311 :ref:`amdgpu-amdhsa-sgpr-register-set-up-order-table`.
8316 :ref:`amdgpu-amdhsa-sgpr-register-set-up-order-table`.
8321 :ref:`amdgpu-amdhsa-sgpr-register-set-up-order-table`.
8326 :ref:`amdgpu-amdhsa-sgpr-register-set-up-order-table`.
8331 :ref:`amdgpu-amdhsa-sgpr-register-set-up-order-table`.
8336 :ref:`amdgpu-amdhsa-sgpr-register-set-up-order-table`.
8483 entries beyond that limit must be fetched from memory (via the spill table
8486 .. table:: PAL Compute Shader User Data Registers
8505 .. table:: PAL Graphics Shader User Data Registers
8521 The placement of the global internal table remains fixed in the first *user
8543 The global internal table is a table of *shader resource descriptors* (SRDs)
8549 The following table illustrates the required format:
8551 .. table:: PAL Global Internal Table
8552 :name: pal-git-table
8573 The pointer to the global internal table passed to the shader as user data
8607 not install a trap handler. The ``llvm.trap`` and ``llvm.debugtrap``
8610 .. table:: AMDGPU Trap Handler for Non-AMDHSA OS
8611 :name: amdgpu-trap-handler-for-non-amdhsa-os-table
8616 llvm.trap s_endpgm Causes wavefront to be terminated.
8617 llvm.debugtrap *none* Compiler warning given that there is no
8634 :ref:`opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table`).
8638 .. table:: OpenCL kernel implicit arguments appended for AMDHSA OS
8639 :name: opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table
8674 This section describes general syntax for instructions and operands.
8679 An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`:
8690 Links to detailed instruction syntax description may be found in the following
8691 table. Note that features under development are not included
9133 :ref:`amdhsa-kernel-directives-table`.
9148 :ref:`amdhsa-kernel-directives-table`.
9183 :ref:`amdhsa-kernel-directives-table`. Directives may appear in any order, must
9191 .. table:: AMDHSA Kernel Assembler Directives
9192 :name: amdhsa-kernel-directives-table
9198 … :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9200 … :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9202 … :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9204 … :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9206 … :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9208 … :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9210 … :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9212 … :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9214 … :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9216 … :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9218 … Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9222 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9224 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9226 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9228 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9230 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9232 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9234 … :ref:`amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table`.
9237 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9240 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9243 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9247 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9250 … Specific :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9253 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9255 … :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
9257 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9259 … :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
9261 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9263 … :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
9265 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9267 … :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
9269 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9271 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9273 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9275 … Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
9279 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9281 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
9283 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9285 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9287 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9289 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9291 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9293 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9295 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
9302 note record (see :ref:`amdgpu-elf-note-records-table-v3-v4`).
9454 .. [CLANG-ATTR] `Attributes in Clang <https://clang.llvm.org/docs/AttributeReference.html>`__