1829     auto AndOp = MIRBuilder.buildAnd(  in widenScalar()
2431   auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask);  in getBitcastWiderVectorElementOffset()
2569   auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask);  in buildBitFieldInsert()
3178     return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0);  in clampDynamicVectorIndex()
4923     auto MIBTmp = MIRBuilder.buildAnd(  in lowerBitCount()
4952     auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0);  in lowerBitCount()
4961     auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0);  in lowerBitCount()
4962     auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0);  in lowerBitCount()
4975     auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0);  in lowerBitCount()
5029   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);  in lowerU64ToF32BitOps()
5032   auto T = MIRBuilder.buildAnd(S64, U, Mask1);  in lowerU64ToF32BitOps()
5043   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);  in lowerU64ToF32BitOps()
5190   auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask);  in lowerFPTOSI()
5195   auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask);  in lowerFPTOSI()
5201   auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask);  in lowerFPTOSI()
5256   E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask));  in lowerFPTRUNC_F64_TO_F16()
5264   M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe));  in lowerFPTRUNC_F64_TO_F16()
5266   auto MaskedSig = MIRBuilder.buildAnd(S32, UH,  in lowerFPTRUNC_F64_TO_F16()
5307   auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7));  in lowerFPTRUNC_F64_TO_F16()
5332   Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000));  in lowerFPTRUNC_F64_TO_F16()
5420   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);  in lowerFCopySign()
5424     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask);  in lowerFCopySign()
5430     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);  in lowerFCopySign()
5436     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);  in lowerFCopySign()
5546   auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc);  in lowerFFloor()
5772     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);  in lowerDynStackAlloc()
5860   auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);  in lowerInsert()
6104     auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);  in lowerBswap()
6109     auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);  in lowerBswap()
6124   auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N);  in SwapN()
6125   auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0);  in SwapN()
6239   auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg);  in lowerSelect()
6240   auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask);  in lowerSelect()