Lines Matching refs:OpNode
1931 SDPatternOperator OpNode>
1934 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
2002 SDNode OpNode>
2004 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
2007 SDNode OpNode>
2009 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
2015 SDNode OpNode, SDNode OpNode_setflags> {
2016 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
2020 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
2039 SDPatternOperator OpNode,
2044 [(set regtype:$Rd, (OpNode in1regtype:$Rn, in2regtype:$Rm))]> {
2057 SDPatternOperator OpNode>
2058 : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
2062 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
2063 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
2067 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
2074 SDPatternOperator OpNode = null_frag>
2075 : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
2080 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
2085 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
2089 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
2093 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
2096 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
2099 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
2102 def : Pat<(i64 (OpNode GPR64:$Rn, (i64 (sext GPR32:$Rm)))),
2106 def : Pat<(i64 (OpNode GPR64:$Rn, (i64 (zext GPR32:$Rm)))),
2157 class MulHi<bits<3> opc, string asm, SDNode OpNode>
2160 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
2188 SDPatternOperator OpNode, string asm>
2191 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
2322 string asm_inst, SDPatternOperator OpNode>
2325 (set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))> {
2333 SDPatternOperator OpNode>
2335 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
2340 SDPatternOperator OpNode>
2343 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
2368 string asm, SDPatternOperator OpNode>
2372 [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
2425 SDPatternOperator OpNode = null_frag> {
2434 mnemonic, OpNode> {
2439 mnemonic, OpNode> {
2444 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
2445 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
2449 OpNode> {
2453 OpNode> {
2461 arith_extended_reg32_i32, mnemonic, OpNode> {
2465 arith_extended_reg32to64_i64, mnemonic, OpNode> {
2505 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
2510 mnemonic, OpNode> {
2514 mnemonic, OpNode> {
2519 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
2520 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
2524 OpNode> {
2528 OpNode> {
2535 arith_extended_reg32_i32, mnemonic, OpNode> {
2539 arith_extended_reg32_i64, mnemonic, OpNode> {
2607 class AddSubG<bit isSub, string asm_inst, SDPatternOperator OpNode>
2611 (set GPR64sp:$Rd, (OpNode GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4))> {
2622 class SUBP<bit setsFlags, string asm_instr, SDPatternOperator OpNode>
2623 : BaseTwoOperand<0b0000, GPR64, asm_instr, OpNode, GPR64sp, GPR64sp> {
2799 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
2803 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
2810 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
2823 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode,
2827 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
2832 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
2845 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
2847 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
2852 SDPatternOperator OpNode> {
2854 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2855 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2859 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
2864 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
2877 SDPatternOperator OpNode = null_frag> {
2879 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2880 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2883 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2887 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2904 string mnemonic, SDNode OpNode>
2907 [(set NZCV, (OpNode regtype:$Rn, immtype:$imm, (i32 imm:$nzcv),
2930 SDNode OpNode>
2933 [(set NZCV, (OpNode regtype:$Rn, regtype:$Rm, (i32 imm:$nzcv),
2954 multiclass CondComparison<bit op, string mnemonic, SDNode OpNode> {
2956 def Wi : BaseCondComparisonImm<op, GPR32, imm32_0_31, mnemonic, OpNode> {
2959 def Xi : BaseCondComparisonImm<op, GPR64, imm0_31, mnemonic, OpNode> {
2963 def Wr : BaseCondComparisonReg<op, GPR32, mnemonic, OpNode> {
2966 def Xr : BaseCondComparisonReg<op, GPR64, mnemonic, OpNode> {
5064 SDPatternOperator OpNode = null_frag> {
5067 [(OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm)), (implicit NZCV)]> {
5073 [(OpNode (f16 FPR16:$Rn), fpimm0), (implicit NZCV)]> {
5079 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
5084 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
5089 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
5094 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
5129 SDPatternOperator OpNode = null_frag> {
5131 [(set NZCV, (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm), (i32 imm:$nzcv),
5138 [(set NZCV, (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm), (i32 imm:$nzcv),
5144 [(set NZCV, (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm), (i32 imm:$nzcv),
5286 multiclass SIMDLogicalThreeVectorPseudo<SDPatternOperator OpNode> {
5289 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5292 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
5295 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
5299 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
5303 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
5308 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
5312 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
5316 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
5324 SDPatternOperator OpNode> {
5327 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5330 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
5333 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5336 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5339 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5342 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5345 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
5348 multiclass SIMDThreeSameVectorExtraPatterns<string inst, SDPatternOperator OpNode> {
5349 def : Pat<(v8i8 (OpNode V64:$LHS, V64:$RHS)),
5351 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
5353 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
5356 def : Pat<(v16i8 (OpNode V128:$LHS, V128:$RHS)),
5358 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
5360 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
5362 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
5368 SDPatternOperator OpNode> {
5371 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
5374 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
5377 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
5380 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
5383 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
5386 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
5390 SDPatternOperator OpNode> {
5394 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5398 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
5402 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5406 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5410 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5414 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5419 SDPatternOperator OpNode> {
5422 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5426 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
5431 string asm, SDPatternOperator OpNode> {
5435 [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
5438 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
5442 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
5445 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
5448 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
5453 SDPatternOperator OpNode> {
5457 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
5460 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
5464 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
5467 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
5470 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
5474 string asm, SDPatternOperator OpNode> {
5479 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
5483 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
5488 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
5492 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
5496 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
5501 SDPatternOperator OpNode> {
5504 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5507 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5510 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5513 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5518 SDPatternOperator OpNode = null_frag> {
5521 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
5524 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
5526 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
5528 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
5530 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
5533 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
5535 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
5537 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
5542 string asm, SDPatternOperator OpNode = null_frag> {
5546 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5550 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
5553 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
5557 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
5561 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
5566 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
5570 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
5574 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
5585 SDPatternOperator OpNode> :
5588 (OpNode (AccumType RegType:$Rd),
5594 multiclass SIMDThreeSameVectorDot<bit U, bit Mixed, string asm, SDPatternOperator OpNode> {
5596 v2i32, v8i8, OpNode>;
5598 v4i32, v16i8, OpNode>;
5607 SDPatternOperator OpNode> :
5610 (OpNode (AccumType RegType:$Rd),
5618 SDPatternOperator OpNode> {
5620 v2f32, v4f16, OpNode>;
5622 v4f32, v8f16, OpNode>;
5681 SDPatternOperator OpNode> {
5684 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
5687 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
5690 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
5693 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
5696 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
5699 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
5739 SDPatternOperator OpNode> {
5742 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
5745 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
5748 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
5751 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
5754 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
5757 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
5761 SDPatternOperator OpNode> {
5764 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
5768 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
5772 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
5776 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
5780 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
5784 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
5790 SDPatternOperator OpNode> {
5793 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
5796 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
5799 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
5802 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
5805 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
5808 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
5811 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
5815 SDPatternOperator OpNode = null_frag> {
5818 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
5821 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
5824 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
5827 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
5830 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
5833 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
5836 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
5842 SDPatternOperator OpNode> {
5845 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
5848 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
5854 SDPatternOperator OpNode> {
5857 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
5860 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
5863 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
5866 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
5872 SDPatternOperator OpNode> {
5876 [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
5879 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
5883 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
5886 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
5889 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
5894 SDPatternOperator OpNode = null_frag> {
5898 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
5901 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
5904 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
5908 SDPatternOperator OpNode = null_frag> :
5909 SIMDTwoVectorSD<U, {0b1111,op}, asm, OpNode>;
5913 SDPatternOperator OpNode> {
5916 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
5919 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
5924 SDPatternOperator OpNode> {
5928 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
5931 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
5935 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
5938 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
5941 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
5945 SDPatternOperator OpNode> {
5949 [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
5952 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
5956 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
5959 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
5962 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
6011 SDPatternOperator OpNode> {
6014 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6019 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6024 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
6028 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
6031 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
6034 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
6042 ValueType sty, SDNode OpNode>
6046 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
6066 SDNode OpNode> {
6069 v8i8, v8i8, OpNode>;
6072 v16i8, v16i8, OpNode>;
6075 v4i16, v4i16, OpNode>;
6078 v8i16, v8i16, OpNode>;
6081 v2i32, v2i32, OpNode>;
6084 v4i32, v4i32, OpNode>;
6087 v2i64, v2i64, OpNode>;
6092 string asm, SDNode OpNode> {
6097 v4i16, v4f16, OpNode>;
6100 v8i16, v8f16, OpNode>;
6104 v2i32, v2f32, OpNode>;
6107 v4i32, v4f32, OpNode>;
6110 v2i64, v2f64, OpNode>;
6204 Intrinsic OpNode> {
6207 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
6211 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
6347 SDPatternOperator OpNode> {
6351 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
6355 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
6360 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
6364 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
6369 SDPatternOperator OpNode = null_frag> {
6374 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
6379 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
6385 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
6390 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
6396 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
6401 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
6407 SDPatternOperator OpNode> {
6413 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
6419 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
6426 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
6432 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
6439 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
6445 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
6450 SDPatternOperator OpNode = null_frag> {
6454 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
6458 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
6463 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
6467 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
6472 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
6476 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
6482 SDPatternOperator OpNode> {
6487 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
6492 (OpNode (v8i16 V128:$Rd),
6499 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
6504 (OpNode (v4i32 V128:$Rd),
6511 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
6516 (OpNode (v2i64 V128:$Rd),
6554 SDPatternOperator OpNode> {
6558 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
6562 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
6567 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
6571 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
6576 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
6580 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
6624 string asm, string kind, SDNode OpNode, ValueType valty>
6628 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
6647 SDNode OpNode> {
6649 asm, ".8b", OpNode, v8i8>;
6651 asm, ".16b", OpNode, v16i8>;
6653 asm, ".4h", OpNode, v4i16>;
6655 asm, ".8h", OpNode, v8i16>;
6657 asm, ".2s", OpNode, v2i32>;
6659 asm, ".4s", OpNode, v4i32>;
6661 asm, ".2d", OpNode, v2i64>;
6663 def : Pat<(v4f16 (OpNode V64:$Rn, V64:$Rm)),
6665 def : Pat<(v8f16 (OpNode V128:$Rn, V128:$Rm)),
6667 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
6669 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
6671 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
6722 SDPatternOperator OpNode> {
6724 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
6728 SDPatternOperator OpNode> {
6730 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
6735 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6737 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
6742 SDPatternOperator OpNode> {
6744 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
6749 SDPatternOperator OpNode = null_frag> {
6759 SDPatternOperator OpNode = null_frag> {
6762 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
6764 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
6767 [(set (f16 FPR16:$Rd), (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm)))]>;
6771 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
6776 SDPatternOperator OpNode = null_frag> {
6779 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
6781 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
6788 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
6814 SDPatternOperator OpNode = null_frag> {
6821 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
6826 SDPatternOperator OpNode = null_frag> {
6836 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
6921 SDPatternOperator OpNode> {
6924 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
6929 SDPatternOperator OpNode> {
6945 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
6950 SDPatternOperator OpNode = null_frag> {
6952 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
6954 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
6967 SDPatternOperator OpNode> {
6969 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
6971 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
6974 [(set (f16 FPR16:$Rd), (OpNode (f16 FPR16:$Rn)))]>;
6979 SDPatternOperator OpNode = null_frag> {
6982 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
6984 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
6989 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
6994 Intrinsic OpNode> {
6997 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
6999 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
7004 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
7012 SDPatternOperator OpNode = null_frag> {
7014 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
7161 ValueType elttype, SDNode OpNode>
7166 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
7715 SDNode OpNode> {
7718 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
7723 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
7729 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
7734 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
7886 class SIMDBF16MLAL<bit Q, string asm, SDPatternOperator OpNode>
7888 [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
7894 class SIMDBF16MLALIndex<bit Q, string asm, SDPatternOperator OpNode>
7899 (v4f32 (OpNode (v4f32 V128:$Rd),
7961 class SIMDThreeSameVectorMatMul<bit B, bit U, string asm, SDPatternOperator OpNode>
7963 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
7975 SDPatternOperator OpNode> :
7979 (AccumType (OpNode (AccumType RegType:$Rd),
7990 SDPatternOperator OpNode> {
7992 V64, v2i32, v8i8, OpNode>;
7994 V128, v4i32, v16i8, OpNode>;
8002 SDPatternOperator OpNode> :
8006 (AccumType (OpNode (AccumType RegType:$Rd),
8018 SDPatternOperator OpNode> {
8020 V64, v2f32, v4f16, OpNode>;
8022 V128, v4f32, v8f16, OpNode>;
8026 SDPatternOperator OpNode> {
8033 (OpNode (v4f16 V64:$Rn),
8046 (OpNode (v8f16 V128:$Rn),
8060 (OpNode (v2f32 V64:$Rn),
8072 (OpNode (v4f32 V128:$Rn),
8084 (OpNode (v2f64 V128:$Rn),
8096 (OpNode (f16 FPR16Op:$Rn),
8110 (OpNode (f32 FPR32Op:$Rn),
8122 (OpNode (f64 FPR64Op:$Rn),
8131 multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
8134 def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
8139 def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
8144 def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn),
8149 def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn),
8154 def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn),
8161 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
8166 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
8173 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
8178 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
8184 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
8189 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
8195 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
8201 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
8342 SDPatternOperator OpNode> {
8347 (OpNode (v4i16 V64:$Rn),
8360 (OpNode (v8i16 V128:$Rn),
8373 (OpNode (v2i32 V64:$Rn),
8385 (OpNode (v4i32 V128:$Rn),
8405 (OpNode FPR32Op:$Rn,
8415 SDPatternOperator OpNode> {
8421 (OpNode (v4i16 V64:$Rn),
8434 (OpNode (v8i16 V128:$Rn),
8447 (OpNode (v2i32 V64:$Rn),
8459 (OpNode (v4i32 V128:$Rn),
8468 SDPatternOperator OpNode> {
8473 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
8486 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
8499 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
8511 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8520 SDPatternOperator OpNode> {
8526 (OpNode (v4i16 V64:$Rn),
8539 (OpNode (extract_high_v8i16 V128:$Rn),
8554 (OpNode (v2i32 V64:$Rn),
8566 (OpNode (extract_high_v4i32 V128:$Rn),
8699 SDPatternOperator OpNode> {
8706 (OpNode (v4i16 V64:$Rn),
8719 (OpNode (extract_high_v8i16 V128:$Rn),
8734 (OpNode (v2i32 V64:$Rn),
8746 (OpNode (extract_high_v4i32 V128:$Rn),
8757 SDPatternOperator OpNode> {
8764 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
8777 (OpNode (v4i32 V128:$Rd),
8792 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
8804 (OpNode (v2i64 V128:$Rd),
8878 SDPatternOperator OpNode> {
8882 (OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
8886 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
8891 SDPatternOperator OpNode = null_frag> {
8894 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
8899 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
8906 SDPatternOperator OpNode> {
8910 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
8925 SDPatternOperator OpNode = null_frag> {
8938 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
8944 SDPatternOperator OpNode> {
8957 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
8963 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
8967 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
9044 Intrinsic OpNode> {
9049 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (i32 imm:$imm)))]> {
9057 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (i32 imm:$imm)))]> {
9065 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
9073 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
9081 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
9088 Intrinsic OpNode> {
9093 [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (i32 imm:$imm)))]> {
9101 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (i32 imm:$imm)))]> {
9110 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
9118 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
9126 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
9133 SDPatternOperator OpNode> {
9137 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
9153 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
9169 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
9187 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
9192 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
9197 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
9205 SDPatternOperator OpNode> {
9209 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
9218 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
9227 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
9236 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
9245 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
9254 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
9263 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
9271 SDPatternOperator OpNode> {
9275 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
9284 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
9293 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
9302 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
9311 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
9320 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
9329 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
9338 SDPatternOperator OpNode = null_frag> {
9342 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
9351 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
9360 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
9369 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
9378 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
9387 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
9396 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
9404 SDPatternOperator OpNode = null_frag> {
9409 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
9419 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
9429 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
9439 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
9449 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
9459 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
9469 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
9477 SDPatternOperator OpNode> {
9480 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
9489 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
9496 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
9505 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
9513 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
9522 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
10599 string asm, SDPatternOperator OpNode>{
10603 [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
10610 [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd),
10619 [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
10626 [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
10633 [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
10671 SDPatternOperator OpNode> {
10675 [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
10682 [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd),
10691 [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
10698 [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
10705 [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
10753 string asm, SDPatternOperator OpNode> {
10801 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
10803 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
10805 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
10809 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
10830 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
10834 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
10837 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
10841 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
10844 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
10848 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
10867 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
10871 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
10873 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
10875 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;