187   bool processSeqRegInst(MachineInstr *DefiningMI, unsigned* StReg,
508   unsigned StReg[4], StRegKill[4];  in optimizeLdStInterleave()  local
524       if (!processSeqRegInst(DefiningMI, StReg, StRegKill, NumReg))  in optimizeLdStInterleave()
566         .addReg(StReg[0])  in optimizeLdStInterleave()
567         .addReg(StReg[1]);  in optimizeLdStInterleave()
569         .addReg(StReg[0], StRegKill[0])  in optimizeLdStInterleave()
570         .addReg(StReg[1], StRegKill[1]);  in optimizeLdStInterleave()
588         .addReg(StReg[0])  in optimizeLdStInterleave()
589         .addReg(StReg[2]);  in optimizeLdStInterleave()
591         .addReg(StReg[0], StRegKill[0])  in optimizeLdStInterleave()
592         .addReg(StReg[2], StRegKill[2]);  in optimizeLdStInterleave()
594         .addReg(StReg[1])  in optimizeLdStInterleave()
595         .addReg(StReg[3]);  in optimizeLdStInterleave()
597         .addReg(StReg[1], StRegKill[1])  in optimizeLdStInterleave()
598         .addReg(StReg[3], StRegKill[3]);  in optimizeLdStInterleave()
635      unsigned* StReg, unsigned* StRegKill, unsigned NumArg) const {  in processSeqRegInst()  argument
641     StReg[i]     = DefiningMI->getOperand(2*i+1).getReg();  in processSeqRegInst()