Lines Matching refs:getSubReg
312 Reg = TRI->getSubReg(Reg, SubReg); in getPhysRegBank()
314 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getPhysRegBank()
316 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getPhysRegBank()
339 Reg = TRI->getSubReg(Reg, SubReg); in getRegBankMask()
351 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getRegBankMask()
416 if (Op.getSubReg()) { in analyzeInst()
417 LaneBitmask LM = TRI->getSubRegIndexLaneMask(Op.getSubReg()); in analyzeInst()
429 if (Bank != -1 && R == Reg && (Op.getSubReg() || SubReg)) { in analyzeInst()
433 Op.getSubReg() ? Op.getSubReg() : (unsigned)AMDGPU::sub0); in analyzeInst()
444 uint32_t Mask = getRegBankMask(R, Op.getSubReg(), in analyzeInst()
448 OperandMasks.push_back(OperandMask(Op.getReg(), Op.getSubReg(), Mask)); in analyzeInst()
510 PhysReg = TRI->getSubReg(PhysReg, AMDGPU::sub0); in isReassignable()