3383   const MCInstrDesc &InstDesc = MI.getDesc();  in isImmOperandLegal()  local
3384   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];  in isImmOperandLegal()
3405   if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))  in isImmOperandLegal()
4452   const MCInstrDesc &InstDesc = MI.getDesc();  in isOperandLegal()  local
4453   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];  in isOperandLegal()
4476             usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {  in isOperandLegal()
4481       } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {  in isOperandLegal()
4484       } else if (isVOP3(MI) && AMDGPU::isSISrcOperand(InstDesc, i) &&  in isOperandLegal()
4485                  isLiteralConstantLike(Op, InstDesc.OpInfo[i])) {  in isOperandLegal()
6039   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitUnaryOp()  local
6054   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);  in splitScalar64BitUnaryOp()
6060   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);  in splitScalar64BitUnaryOp()
6166   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitBinaryOp()  local
6192   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)  in splitScalar64BitBinaryOp()
6197   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)  in splitScalar64BitBinaryOp()
6270   const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);  in splitScalar64BitBCNT()  local
6285   BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);  in splitScalar64BitBCNT()
6287   BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);  in splitScalar64BitBCNT()