134     const MachineOperand *AddrReg[MaxAddressRegs];  member
142         if (AddrReg[i]->isImm() || AddrRegNext.isImm()) {  in hasSameBaseAddress()
143           if (AddrReg[i]->isImm() != AddrRegNext.isImm() ||  in hasSameBaseAddress()
144               AddrReg[i]->getImm() != AddrRegNext.getImm()) {  in hasSameBaseAddress()
152         if (AddrReg[i]->getReg() != AddrRegNext.getReg() ||  in hasSameBaseAddress()
153             AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) {  in hasSameBaseAddress()
162         const MachineOperand *AddrOp = AddrReg[i];  in hasMergeableAddress()
580     AddrReg[J] = &I->getOperand(AddrIdx[J]);  in setMI()
1015   const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr);  in mergeRead2Pair()  local
1045   Register BaseReg = AddrReg->getReg();  in mergeRead2Pair()
1046   unsigned BaseSubReg = AddrReg->getSubReg();  in mergeRead2Pair()
1058         .addReg(AddrReg->getReg(), 0, BaseSubReg)  in mergeRead2Pair()
1115   const MachineOperand *AddrReg =  in mergeWrite2Pair()  local
1139   Register BaseReg = AddrReg->getReg();  in mergeWrite2Pair()
1140   unsigned BaseSubReg = AddrReg->getSubReg();  in mergeWrite2Pair()
1152         .addReg(AddrReg->getReg(), 0, BaseSubReg)  in mergeWrite2Pair()