Lines Matching refs:N2RegVShRFrm

3170            (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3182            (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3190            (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3944 //   with f of either N2RegVShLFrm or N2RegVShRFrm
3987   def v8i8  : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3991   def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3995   def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3999   def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
4004   def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
4008   def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
4012   def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
4016   def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
4061 //   with f of either N2RegVShLFrm or N2RegVShRFrm
4103                         N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsriImm> {
4107                         N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsriImm> {
4111                         N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsriImm> {
4115                         N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsriImm>;
4120                         N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsriImm> {
4124                         N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsriImm> {
4128                         N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsriImm> {
4132                         N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsriImm>;