Lines Matching refs:Sched
392 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
405 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
425 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
436 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
457 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
469 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
485 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
494 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
504 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
508 [(ARMseretflag)]>, Sched<[WriteBr]>;
513 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
526 Requires<[IsThumb]>, Sched<[WriteBrL]> {
539 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
554 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
564 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> {
573 Requires<[IsThumb, Has8MSecExt]>, Sched<[WriteBr]>;
579 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
586 Requires<[IsThumb]>, Sched<[WriteBr]>;
593 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
606 Sched<[WriteBrTbl]>;
612 Sched<[WriteBrTbl]> {
625 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
641 Requires<[IsThumb]>, Sched<[WriteBr]>;
651 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>;
661 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
671 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
686 T1Encoding<{0,1,0,0,1,?}>, Sched<[WriteLd]> {
700 T1LdStSP<{1,?,?}>, Sched<[WriteLd]> {
751 load>, Sched<[WriteLd]>;
757 zextloadi8>, Sched<[WriteLd]>;
763 zextloadi16>, Sched<[WriteLd]>;
770 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr_sext:$addr))]>, Sched<[WriteLd]>;
777 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr_sext:$addr))]>, Sched<[WriteLd]>;
783 T1LdStSP<{0,?,?}>, Sched<[WriteST]> {
794 store>, Sched<[WriteST]>;
800 truncstorei8>, Sched<[WriteST]>;
806 truncstorei16>, Sched<[WriteST]>;
866 T1Misc<{1,1,0,?,?,?,?}>, Sched<[WriteLd]> {
876 T1Misc<{0,1,0,?,?,?,?}>, Sched<[WriteST]> {
963 []>, Sched<[WriteALU]>;
971 Sched<[WriteALU]> {
981 Sched<[WriteALU]>;
989 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1003 Sched<[WriteALU]>;
1010 Sched<[WriteALU]>;
1017 Sched<[WriteALU]>;
1025 Sched<[WriteALU]>;
1031 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
1065 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1073 Sched<[WriteALU]> {
1083 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1091 Sched<[WriteALU]>;
1107 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
1116 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
1129 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
1133 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
1150 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1158 Sched<[WriteALU]> {
1168 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1176 Sched<[WriteALU]> {
1186 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1193 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1211 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1221 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1237 T1DataProcessing<0b1101>, Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
1252 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1260 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1268 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1275 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1282 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1290 Sched<[WriteALU]>;
1297 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1306 Sched<[WriteALU]>;
1314 Sched<[WriteALU]> {
1324 Sched<[WriteALU]>;
1340 Sched<[WriteALU]>;
1357 Sched<[WriteALU]>;
1364 Sched<[WriteALU]>;
1371 Sched<[WriteALU]>;
1378 Sched<[WriteALU]>;
1384 Sched<[WriteALU]>;
1390 Sched<[WriteALU]>;
1406 Sched<[WriteALU]>;
1415 Sched<[WriteALU]>;
1423 Sched<[WriteALU]>;
1451 Sched<[WriteALU]>;
1459 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1474 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1484 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1489 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1497 IIC_Br, []>, Sched<[WriteBr]>;
1501 IIC_Br, []>, Sched<[WriteBr]>;
1514 Sched<[WriteBr]>;
1731 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1737 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;