Lines Matching refs:SrcLoReg
144 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expandArith() local
151 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandArith()
157 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
177 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expandLogic() local
184 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandLogic()
190 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
459 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expand() local
467 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
473 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
492 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expand() local
500 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
505 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
1009 Register SrcLoReg, SrcHiReg; in expand() local
1014 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1042 MIBLO.addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
1055 Register SrcLoReg, SrcHiReg; in expand() local
1061 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1066 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
1083 Register SrcLoReg, SrcHiReg; in expand() local
1091 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1098 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1117 Register SrcLoReg, SrcHiReg; in expand() local
1125 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1138 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1151 Register SrcLoReg, SrcHiReg; in expand() local
1159 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1168 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
1215 Register SrcLoReg, SrcHiReg; in expand() local
1221 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1234 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
1246 Register SrcLoReg, SrcHiReg; in expand() local
1252 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1256 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1604 Register SrcLoReg, SrcHiReg; in expand() local
1608 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1629 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()