Lines Matching refs:Pat
12 : Pat <(IntID I32:$Rs),
16 : Pat <(IntID I32:$Rs, I32:$Rt),
20 : Pat <(IntID I32:$Rs, I64:$Rt),
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
27 def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt),
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
32 def: Pat<(int_hexagon_A2_subri timm:$s10, IntRegs:$Rs),
34 def: Pat<(int_hexagon_A2_subp DoubleRegs:$Rs, DoubleRegs:$Rt),
37 def: Pat<(int_hexagon_M2_mpyi IntRegs:$Rs, IntRegs:$Rt),
39 def: Pat<(int_hexagon_M2_mpyui IntRegs:$Rs, IntRegs:$Rt), // Same as M2_mpyi
41 def: Pat<(int_hexagon_M2_mpysmi IntRegs:$Rs, imm:$s9),
43 def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$Rs, IntRegs:$Rt),
45 def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$Rs, IntRegs:$Rt),
48 def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$Rs, timm:$u5),
50 def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$Rs, timm:$u5),
52 def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$Rs, timm:$u5),
54 def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$Rs, timm:$u6),
56 def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$Rs, timm:$u6),
58 def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$Rs, timm:$u6),
61 def: Pat<(int_hexagon_A2_and IntRegs:$Rs, IntRegs:$Rt),
63 def: Pat<(int_hexagon_A2_andir IntRegs:$Rs, timm:$s10),
65 def: Pat<(int_hexagon_A2_or IntRegs:$Rs, IntRegs:$Rt),
67 def: Pat<(int_hexagon_A2_orir IntRegs:$Rs, timm:$s10),
69 def: Pat<(int_hexagon_A2_xor IntRegs:$Rs, IntRegs:$Rt),
72 def: Pat<(int_hexagon_A2_sxtb IntRegs:$Rs),
74 def: Pat<(int_hexagon_A2_sxth IntRegs:$Rs),
76 def: Pat<(int_hexagon_A2_zxtb IntRegs:$Rs),
78 def: Pat<(int_hexagon_A2_zxth IntRegs:$Rs),
82 def : Pat <(int_hexagon_A2_not I32:$Rs),
86 def : Pat <(int_hexagon_A2_neg I32:$Rs),
92 def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, (i32 0)),
94 def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, (i32 0)),
96 def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, (i32 0)),
98 def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, (i32 0)),
102 def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, u5_0ImmPred_timm:$imm),
104 def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, u6_0ImmPred_timm:$imm),
106 def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, u4_0ImmPred_timm:$imm),
108 def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, u4_0ImmPred_timm:$imm),
124 def : Pat<(int_hexagon_A2_tfrpi timm:$Is),
127 def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred_timm:$src2),
130 def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32_0ImmPred_timm:$src2),
133 def : Pat <(int_hexagon_C2_cmpgeui I32:$src, 0),
135 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
137 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
177 def : Pat<(int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt),
179 def : Pat<(int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt),
187 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
197 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
207 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
211 def : Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2,
239 def: Pat<(int_hexagon_Y2_dcfetch I32:$Rt), (Y2_dcfetchbo I32:$Rt, 0)>;
265 def : Pat <(v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
269 def : Pat <(v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
273 def : Pat <(v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
277 def : Pat <(v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
282 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
289 def: Pat<(IntID HvxVR:$src1, u3_0ImmPred:$src2),
293 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, u3_0ImmPred:$src2),
299 def: Pat<(IntID HvxVR:$src1, u3_64_ImmPred:$src2),
304 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, u3_128_ImmPred:$src2),
310 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3),
314 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
322 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_64_ImmPred:$src3),
327 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
335 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
339 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
358 def: Pat<(int_hexagon_V6_vd0),
360 def: Pat<(int_hexagon_V6_vd0_128B ),
363 def: Pat<(int_hexagon_V6_vdd0),
365 def: Pat<(int_hexagon_V6_vdd0_128B),
368 def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
370 def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
372 def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
374 def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
376 def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:…
378 def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:…
380 def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
382 def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
384 def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR…
386 def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
388 def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
390 def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4…
392 def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4…
394 def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, H…
396 def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, H…
398 def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
400 def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src…
402 def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, …