Lines Matching refs:Mips
122 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
123 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
124 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
125 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
126 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
127 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
128 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
129 Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
130 Mips::FeatureNaN2008
577 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit]; in isGP64bit()
581 return getSTI().getFeatureBits()[Mips::FeatureFP64Bit]; in isFP64bit()
602 return getSTI().getFeatureBits()[Mips::FeatureFPXX]; in isABI_FPXX()
606 return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]); in useOddSPReg()
610 return getSTI().getFeatureBits()[Mips::FeatureMicroMips]; in inMicroMipsMode()
614 return getSTI().getFeatureBits()[Mips::FeatureMips1]; in hasMips1()
618 return getSTI().getFeatureBits()[Mips::FeatureMips2]; in hasMips2()
622 return getSTI().getFeatureBits()[Mips::FeatureMips3]; in hasMips3()
626 return getSTI().getFeatureBits()[Mips::FeatureMips4]; in hasMips4()
630 return getSTI().getFeatureBits()[Mips::FeatureMips5]; in hasMips5()
634 return getSTI().getFeatureBits()[Mips::FeatureMips32]; in hasMips32()
638 return getSTI().getFeatureBits()[Mips::FeatureMips64]; in hasMips64()
642 return getSTI().getFeatureBits()[Mips::FeatureMips32r2]; in hasMips32r2()
646 return getSTI().getFeatureBits()[Mips::FeatureMips64r2]; in hasMips64r2()
650 return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]); in hasMips32r3()
654 return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]); in hasMips64r3()
658 return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]); in hasMips32r5()
662 return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]); in hasMips64r5()
666 return getSTI().getFeatureBits()[Mips::FeatureMips32r6]; in hasMips32r6()
670 return getSTI().getFeatureBits()[Mips::FeatureMips64r6]; in hasMips64r6()
674 return getSTI().getFeatureBits()[Mips::FeatureDSP]; in hasDSP()
678 return getSTI().getFeatureBits()[Mips::FeatureDSPR2]; in hasDSPR2()
682 return getSTI().getFeatureBits()[Mips::FeatureDSPR3]; in hasDSPR3()
686 return getSTI().getFeatureBits()[Mips::FeatureMSA]; in hasMSA()
690 return (getSTI().getFeatureBits()[Mips::FeatureCnMips]); in hasCnMips()
694 return (getSTI().getFeatureBits()[Mips::FeatureCnMipsP]); in hasCnMipsP()
702 return getSTI().getFeatureBits()[Mips::FeatureMips16]; in inMips16Mode()
706 return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV]; in useTraps()
710 return getSTI().getFeatureBits()[Mips::FeatureSoftFloat]; in useSoftFloat()
713 return getSTI().getFeatureBits()[Mips::FeatureMT]; in hasMT()
717 return getSTI().getFeatureBits()[Mips::FeatureCRC]; in hasCRC()
721 return getSTI().getFeatureBits()[Mips::FeatureVirt]; in hasVirt()
725 return getSTI().getFeatureBits()[Mips::FeatureGINV]; in hasGINV()
910 unsigned ClassID = Mips::GPR32RegClassID; in getGPR32Reg()
918 unsigned ClassID = Mips::GPR32RegClassID; in getGPRMM16Reg()
926 unsigned ClassID = Mips::GPR64RegClassID; in getGPR64Reg()
937 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID) in getAFGR64Reg()
945 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID) in getFGR64Reg()
953 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID) in getFGR32Reg()
961 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID) in getFCCReg()
971 unsigned ClassID = Mips::MSA128BRegClassID; in getMSA128Reg()
979 unsigned ClassID = Mips::MSACtrlRegClassID; in getMSACtrlReg()
987 unsigned ClassID = Mips::COP0RegClassID; in getCOP0Reg()
995 unsigned ClassID = Mips::COP2RegClassID; in getCOP2Reg()
1003 unsigned ClassID = Mips::COP3RegClassID; in getCOP3Reg()
1011 unsigned ClassID = Mips::ACC64DSPRegClassID; in getACC64DSPReg()
1019 unsigned ClassID = Mips::HI32DSPRegClassID; in getHI32DSPReg()
1027 unsigned ClassID = Mips::LO32DSPRegClassID; in getLO32DSPReg()
1035 unsigned ClassID = Mips::CCRRegClassID; in getCCRReg()
1043 unsigned ClassID = Mips::HWRegsRegClassID; in getHWRegsReg()
1373 && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP); in isMemWithUimmOffsetSP()
1379 && (getMemBase()->getGPR32Reg() == Mips::SP); in isMemWithUimmWordAlignedOffsetSP()
1385 && (getMemBase()->getGPR32Reg() == Mips::GP); in isMemWithSimmWordAlignedOffsetGP()
1418 if (!((R0 == Mips::S0 && R1 == Mips::RA) || in isRegList16()
1419 (R0 == Mips::S0_64 && R1 == Mips::RA_64))) in isRegList16()
1760 case Mips::BEQ_MM: in hasShortDelaySlot()
1761 case Mips::BNE_MM: in hasShortDelaySlot()
1762 case Mips::BLTZ_MM: in hasShortDelaySlot()
1763 case Mips::BGEZ_MM: in hasShortDelaySlot()
1764 case Mips::BLEZ_MM: in hasShortDelaySlot()
1765 case Mips::BGTZ_MM: in hasShortDelaySlot()
1766 case Mips::JRC16_MM: in hasShortDelaySlot()
1767 case Mips::JALS_MM: in hasShortDelaySlot()
1768 case Mips::JALRS_MM: in hasShortDelaySlot()
1769 case Mips::JALRS16_MM: in hasShortDelaySlot()
1770 case Mips::BGEZALS_MM: in hasShortDelaySlot()
1771 case Mips::BLTZALS_MM: in hasShortDelaySlot()
1773 case Mips::J_MM: in hasShortDelaySlot()
1888 case Mips::BBIT0: in processInstruction()
1889 case Mips::BBIT032: in processInstruction()
1890 case Mips::BBIT1: in processInstruction()
1891 case Mips::BBIT132: in processInstruction()
1895 case Mips::BEQ: in processInstruction()
1896 case Mips::BNE: in processInstruction()
1897 case Mips::BEQ_MM: in processInstruction()
1898 case Mips::BNE_MM: in processInstruction()
1909 case Mips::BGEZ: in processInstruction()
1910 case Mips::BGTZ: in processInstruction()
1911 case Mips::BLEZ: in processInstruction()
1912 case Mips::BLTZ: in processInstruction()
1913 case Mips::BGEZAL: in processInstruction()
1914 case Mips::BLTZAL: in processInstruction()
1915 case Mips::BC1F: in processInstruction()
1916 case Mips::BC1T: in processInstruction()
1917 case Mips::BGEZ_MM: in processInstruction()
1918 case Mips::BGTZ_MM: in processInstruction()
1919 case Mips::BLEZ_MM: in processInstruction()
1920 case Mips::BLTZ_MM: in processInstruction()
1921 case Mips::BGEZAL_MM: in processInstruction()
1922 case Mips::BLTZAL_MM: in processInstruction()
1923 case Mips::BC1F_MM: in processInstruction()
1924 case Mips::BC1T_MM: in processInstruction()
1925 case Mips::BC1EQZC_MMR6: in processInstruction()
1926 case Mips::BC1NEZC_MMR6: in processInstruction()
1927 case Mips::BC2EQZC_MMR6: in processInstruction()
1928 case Mips::BC2NEZC_MMR6: in processInstruction()
1939 case Mips::BGEC: case Mips::BGEC_MMR6: in processInstruction()
1940 case Mips::BLTC: case Mips::BLTC_MMR6: in processInstruction()
1941 case Mips::BGEUC: case Mips::BGEUC_MMR6: in processInstruction()
1942 case Mips::BLTUC: case Mips::BLTUC_MMR6: in processInstruction()
1943 case Mips::BEQC: case Mips::BEQC_MMR6: in processInstruction()
1944 case Mips::BNEC: case Mips::BNEC_MMR6: in processInstruction()
1954 case Mips::BLEZC: case Mips::BLEZC_MMR6: in processInstruction()
1955 case Mips::BGEZC: case Mips::BGEZC_MMR6: in processInstruction()
1956 case Mips::BGTZC: case Mips::BGTZC_MMR6: in processInstruction()
1957 case Mips::BLTZC: case Mips::BLTZC_MMR6: in processInstruction()
1967 case Mips::BEQZC: case Mips::BEQZC_MMR6: in processInstruction()
1968 case Mips::BNEZC: case Mips::BNEZC_MMR6: in processInstruction()
1978 case Mips::BEQZ16_MM: in processInstruction()
1979 case Mips::BEQZC16_MMR6: in processInstruction()
1980 case Mips::BNEZ16_MM: in processInstruction()
1981 case Mips::BNEZC16_MMR6: in processInstruction()
1996 if (hasMips32r6() && Opcode == Mips::SSNOP) { in processInstruction()
2010 case Mips::BBIT0: in processInstruction()
2011 case Mips::BBIT032: in processInstruction()
2012 case Mips::BBIT1: in processInstruction()
2013 case Mips::BBIT132: in processInstruction()
2020 if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 || in processInstruction()
2021 Opcode == Mips::BBIT1 ? 63 : 31)) in processInstruction()
2024 Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032 in processInstruction()
2025 : Mips::BBIT132); in processInstruction()
2030 case Mips::SEQi: in processInstruction()
2031 case Mips::SNEi: in processInstruction()
2055 case Mips::SDivIMacro: in processInstruction()
2056 case Mips::UDivIMacro: in processInstruction()
2057 case Mips::DSDivIMacro: in processInstruction()
2058 case Mips::DUDivIMacro: in processInstruction()
2060 if (Inst.getOperand(1).getReg() == Mips::ZERO || in processInstruction()
2061 Inst.getOperand(1).getReg() == Mips::ZERO_64) in processInstruction()
2067 case Mips::DSDIV: in processInstruction()
2068 case Mips::SDIV: in processInstruction()
2069 case Mips::UDIV: in processInstruction()
2070 case Mips::DUDIV: in processInstruction()
2071 case Mips::UDIV_MM: in processInstruction()
2072 case Mips::SDIV_MM: in processInstruction()
2076 case Mips::SDivMacro: in processInstruction()
2077 case Mips::DSDivMacro: in processInstruction()
2078 case Mips::UDivMacro: in processInstruction()
2079 case Mips::DUDivMacro: in processInstruction()
2080 case Mips::DIV: in processInstruction()
2081 case Mips::DIVU: in processInstruction()
2082 case Mips::DDIV: in processInstruction()
2083 case Mips::DDIVU: in processInstruction()
2084 case Mips::DIVU_MMR6: in processInstruction()
2085 case Mips::DIV_MMR6: in processInstruction()
2086 if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO || in processInstruction()
2087 Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) { in processInstruction()
2088 if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO || in processInstruction()
2089 Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64) in processInstruction()
2098 if ((Opcode == Mips::J || Opcode == Mips::J_MM) && inPicMode()) { in processInstruction()
2100 BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ); in processInstruction()
2101 BInst.addOperand(MCOperand::createReg(Mips::ZERO)); in processInstruction()
2102 BInst.addOperand(MCOperand::createReg(Mips::ZERO)); in processInstruction()
2109 if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) { in processInstruction()
2123 if (expandLoadAddress(Mips::T9, Mips::NoRegister, Inst.getOperand(0), in processInstruction()
2129 JalrInst.setOpcode(IsCpRestoreSet ? Mips::JALRS_MM : Mips::JALR_MM); in processInstruction()
2131 JalrInst.setOpcode(Mips::JALR); in processInstruction()
2132 JalrInst.addOperand(MCOperand::createReg(Mips::RA)); in processInstruction()
2133 JalrInst.addOperand(MCOperand::createReg(Mips::T9)); in processInstruction()
2173 if (MCID.mayLoad() && Opcode != Mips::LWP_MM) { in processInstruction()
2186 Mips::GPRMM16RegClassID).contains(DstReg.getReg()) && in processInstruction()
2187 (BaseReg.getReg() == Mips::GP || in processInstruction()
2188 BaseReg.getReg() == Mips::GP_64)) { in processInstruction()
2190 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset, in processInstruction()
2207 case Mips::ADDIUSP_MM: in processInstruction()
2216 case Mips::SLL16_MM: in processInstruction()
2217 case Mips::SRL16_MM: in processInstruction()
2225 case Mips::LI16_MM: in processInstruction()
2233 case Mips::ADDIUR2_MM: in processInstruction()
2242 case Mips::ANDI16_MM: in processInstruction()
2252 case Mips::LBU16_MM: in processInstruction()
2260 case Mips::SB16_MM: in processInstruction()
2261 case Mips::SB16_MMR6: in processInstruction()
2269 case Mips::LHU16_MM: in processInstruction()
2270 case Mips::SH16_MM: in processInstruction()
2271 case Mips::SH16_MMR6: in processInstruction()
2279 case Mips::LW16_MM: in processInstruction()
2280 case Mips::SW16_MM: in processInstruction()
2281 case Mips::SW16_MMR6: in processInstruction()
2289 case Mips::ADDIUPC_MM: in processInstruction()
2297 case Mips::LWP_MM: in processInstruction()
2298 case Mips::SWP_MM: in processInstruction()
2299 if (Inst.getOperand(0).getReg() == Mips::RA) in processInstruction()
2302 case Mips::MOVEP_MM: in processInstruction()
2303 case Mips::MOVEP_MMR6: { in processInstruction()
2306 bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) || in processInstruction()
2307 (R0 == Mips::A1 && R1 == Mips::A3) || in processInstruction()
2308 (R0 == Mips::A2 && R1 == Mips::A3) || in processInstruction()
2309 (R0 == Mips::A0 && R1 == Mips::S5) || in processInstruction()
2310 (R0 == Mips::A0 && R1 == Mips::S6) || in processInstruction()
2311 (R0 == Mips::A0 && R1 == Mips::A1) || in processInstruction()
2312 (R0 == Mips::A0 && R1 == Mips::A2) || in processInstruction()
2313 (R0 == Mips::A0 && R1 == Mips::A3)); in processInstruction()
2352 if ((Opcode == Mips::JalOneReg || Opcode == Mips::JalTwoReg || in processInstruction()
2378 case Mips::LoadImm32: in tryExpandInstruction()
2380 case Mips::LoadImm64: in tryExpandInstruction()
2382 case Mips::LoadAddrImm32: in tryExpandInstruction()
2383 case Mips::LoadAddrImm64: in tryExpandInstruction()
2388 return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister, in tryExpandInstruction()
2390 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, in tryExpandInstruction()
2394 case Mips::LoadAddrReg32: in tryExpandInstruction()
2395 case Mips::LoadAddrReg64: in tryExpandInstruction()
2403 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc, in tryExpandInstruction()
2407 case Mips::B_MM_Pseudo: in tryExpandInstruction()
2408 case Mips::B_MMR6_Pseudo: in tryExpandInstruction()
2411 case Mips::SWM_MM: in tryExpandInstruction()
2412 case Mips::LWM_MM: in tryExpandInstruction()
2415 case Mips::JalOneReg: in tryExpandInstruction()
2416 case Mips::JalTwoReg: in tryExpandInstruction()
2418 case Mips::BneImm: in tryExpandInstruction()
2419 case Mips::BeqImm: in tryExpandInstruction()
2420 case Mips::BEQLImmMacro: in tryExpandInstruction()
2421 case Mips::BNELImmMacro: in tryExpandInstruction()
2423 case Mips::BLT: in tryExpandInstruction()
2424 case Mips::BLE: in tryExpandInstruction()
2425 case Mips::BGE: in tryExpandInstruction()
2426 case Mips::BGT: in tryExpandInstruction()
2427 case Mips::BLTU: in tryExpandInstruction()
2428 case Mips::BLEU: in tryExpandInstruction()
2429 case Mips::BGEU: in tryExpandInstruction()
2430 case Mips::BGTU: in tryExpandInstruction()
2431 case Mips::BLTL: in tryExpandInstruction()
2432 case Mips::BLEL: in tryExpandInstruction()
2433 case Mips::BGEL: in tryExpandInstruction()
2434 case Mips::BGTL: in tryExpandInstruction()
2435 case Mips::BLTUL: in tryExpandInstruction()
2436 case Mips::BLEUL: in tryExpandInstruction()
2437 case Mips::BGEUL: in tryExpandInstruction()
2438 case Mips::BGTUL: in tryExpandInstruction()
2439 case Mips::BLTImmMacro: in tryExpandInstruction()
2440 case Mips::BLEImmMacro: in tryExpandInstruction()
2441 case Mips::BGEImmMacro: in tryExpandInstruction()
2442 case Mips::BGTImmMacro: in tryExpandInstruction()
2443 case Mips::BLTUImmMacro: in tryExpandInstruction()
2444 case Mips::BLEUImmMacro: in tryExpandInstruction()
2445 case Mips::BGEUImmMacro: in tryExpandInstruction()
2446 case Mips::BGTUImmMacro: in tryExpandInstruction()
2447 case Mips::BLTLImmMacro: in tryExpandInstruction()
2448 case Mips::BLELImmMacro: in tryExpandInstruction()
2449 case Mips::BGELImmMacro: in tryExpandInstruction()
2450 case Mips::BGTLImmMacro: in tryExpandInstruction()
2451 case Mips::BLTULImmMacro: in tryExpandInstruction()
2452 case Mips::BLEULImmMacro: in tryExpandInstruction()
2453 case Mips::BGEULImmMacro: in tryExpandInstruction()
2454 case Mips::BGTULImmMacro: in tryExpandInstruction()
2456 case Mips::SDivMacro: in tryExpandInstruction()
2457 case Mips::SDivIMacro: in tryExpandInstruction()
2458 case Mips::SRemMacro: in tryExpandInstruction()
2459 case Mips::SRemIMacro: in tryExpandInstruction()
2462 case Mips::DSDivMacro: in tryExpandInstruction()
2463 case Mips::DSDivIMacro: in tryExpandInstruction()
2464 case Mips::DSRemMacro: in tryExpandInstruction()
2465 case Mips::DSRemIMacro: in tryExpandInstruction()
2468 case Mips::UDivMacro: in tryExpandInstruction()
2469 case Mips::UDivIMacro: in tryExpandInstruction()
2470 case Mips::URemMacro: in tryExpandInstruction()
2471 case Mips::URemIMacro: in tryExpandInstruction()
2474 case Mips::DUDivMacro: in tryExpandInstruction()
2475 case Mips::DUDivIMacro: in tryExpandInstruction()
2476 case Mips::DURemMacro: in tryExpandInstruction()
2477 case Mips::DURemIMacro: in tryExpandInstruction()
2480 case Mips::PseudoTRUNC_W_S: in tryExpandInstruction()
2483 case Mips::PseudoTRUNC_W_D32: in tryExpandInstruction()
2486 case Mips::PseudoTRUNC_W_D: in tryExpandInstruction()
2490 case Mips::LoadImmSingleGPR: in tryExpandInstruction()
2493 case Mips::LoadImmSingleFGR: in tryExpandInstruction()
2496 case Mips::LoadImmDoubleGPR: in tryExpandInstruction()
2499 case Mips::LoadImmDoubleFGR: in tryExpandInstruction()
2502 case Mips::LoadImmDoubleFGR_32: in tryExpandInstruction()
2506 case Mips::Ulh: in tryExpandInstruction()
2508 case Mips::Ulhu: in tryExpandInstruction()
2510 case Mips::Ush: in tryExpandInstruction()
2512 case Mips::Ulw: in tryExpandInstruction()
2513 case Mips::Usw: in tryExpandInstruction()
2515 case Mips::NORImm: in tryExpandInstruction()
2516 case Mips::NORImm64: in tryExpandInstruction()
2518 case Mips::SGE: in tryExpandInstruction()
2519 case Mips::SGEU: in tryExpandInstruction()
2521 case Mips::SGEImm: in tryExpandInstruction()
2522 case Mips::SGEUImm: in tryExpandInstruction()
2523 case Mips::SGEImm64: in tryExpandInstruction()
2524 case Mips::SGEUImm64: in tryExpandInstruction()
2526 case Mips::SGTImm: in tryExpandInstruction()
2527 case Mips::SGTUImm: in tryExpandInstruction()
2528 case Mips::SGTImm64: in tryExpandInstruction()
2529 case Mips::SGTUImm64: in tryExpandInstruction()
2531 case Mips::SLE: in tryExpandInstruction()
2532 case Mips::SLEU: in tryExpandInstruction()
2534 case Mips::SLEImm: in tryExpandInstruction()
2535 case Mips::SLEUImm: in tryExpandInstruction()
2536 case Mips::SLEImm64: in tryExpandInstruction()
2537 case Mips::SLEUImm64: in tryExpandInstruction()
2539 case Mips::SLTImm64: in tryExpandInstruction()
2541 Inst.setOpcode(Mips::SLTi64); in tryExpandInstruction()
2545 case Mips::SLTUImm64: in tryExpandInstruction()
2547 Inst.setOpcode(Mips::SLTiu64); in tryExpandInstruction()
2551 case Mips::ADDi: case Mips::ADDi_MM: in tryExpandInstruction()
2552 case Mips::ADDiu: case Mips::ADDiu_MM: in tryExpandInstruction()
2553 case Mips::SLTi: case Mips::SLTi_MM: in tryExpandInstruction()
2554 case Mips::SLTiu: case Mips::SLTiu_MM: in tryExpandInstruction()
2564 case Mips::ANDi: case Mips::ANDi_MM: case Mips::ANDi64: in tryExpandInstruction()
2565 case Mips::ORi: case Mips::ORi_MM: case Mips::ORi64: in tryExpandInstruction()
2566 case Mips::XORi: case Mips::XORi_MM: case Mips::XORi64: in tryExpandInstruction()
2576 case Mips::ROL: in tryExpandInstruction()
2577 case Mips::ROR: in tryExpandInstruction()
2579 case Mips::ROLImm: in tryExpandInstruction()
2580 case Mips::RORImm: in tryExpandInstruction()
2582 case Mips::DROL: in tryExpandInstruction()
2583 case Mips::DROR: in tryExpandInstruction()
2585 case Mips::DROLImm: in tryExpandInstruction()
2586 case Mips::DRORImm: in tryExpandInstruction()
2588 case Mips::ABSMacro: in tryExpandInstruction()
2590 case Mips::MULImmMacro: in tryExpandInstruction()
2591 case Mips::DMULImmMacro: in tryExpandInstruction()
2593 case Mips::MULOMacro: in tryExpandInstruction()
2594 case Mips::DMULOMacro: in tryExpandInstruction()
2596 case Mips::MULOUMacro: in tryExpandInstruction()
2597 case Mips::DMULOUMacro: in tryExpandInstruction()
2599 case Mips::DMULMacro: in tryExpandInstruction()
2601 case Mips::LDMacro: in tryExpandInstruction()
2602 case Mips::SDMacro: in tryExpandInstruction()
2604 Inst.getOpcode() == Mips::LDMacro) in tryExpandInstruction()
2607 case Mips::SDC1_M1: in tryExpandInstruction()
2611 case Mips::SEQMacro: in tryExpandInstruction()
2613 case Mips::SEQIMacro: in tryExpandInstruction()
2615 case Mips::SNEMacro: in tryExpandInstruction()
2617 case Mips::SNEIMacro: in tryExpandInstruction()
2619 case Mips::MFTC0: case Mips::MTTC0: in tryExpandInstruction()
2620 case Mips::MFTGPR: case Mips::MTTGPR: in tryExpandInstruction()
2621 case Mips::MFTLO: case Mips::MTTLO: in tryExpandInstruction()
2622 case Mips::MFTHI: case Mips::MTTHI: in tryExpandInstruction()
2623 case Mips::MFTACX: case Mips::MTTACX: in tryExpandInstruction()
2624 case Mips::MFTDSP: case Mips::MTTDSP: in tryExpandInstruction()
2625 case Mips::MFTC1: case Mips::MTTC1: in tryExpandInstruction()
2626 case Mips::MFTHC1: case Mips::MTTHC1: in tryExpandInstruction()
2627 case Mips::CFTC1: case Mips::CTTC1: in tryExpandInstruction()
2629 case Mips::SaaAddr: in tryExpandInstruction()
2630 case Mips::SaadAddr: in tryExpandInstruction()
2646 if (Opcode == Mips::JalOneReg) { in expandJalWithRegs()
2649 JalrInst.setOpcode(Mips::JALRS16_MM); in expandJalWithRegs()
2652 JalrInst.setOpcode(hasMips32r6() ? Mips::JALRC16_MMR6 : Mips::JALR16_MM); in expandJalWithRegs()
2655 JalrInst.setOpcode(Mips::JALR); in expandJalWithRegs()
2656 JalrInst.addOperand(MCOperand::createReg(Mips::RA)); in expandJalWithRegs()
2659 } else if (Opcode == Mips::JalTwoReg) { in expandJalWithRegs()
2662 JalrInst.setOpcode(Mips::JALRS_MM); in expandJalWithRegs()
2664 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR); in expandJalWithRegs()
2722 unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu; in loadImmediate()
2725 if (SrcReg != Mips::NoRegister) in loadImmediate()
2747 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2751 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2763 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2778 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2779 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2787 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2788 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in loadImmediate()
2790 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2796 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI); in loadImmediate()
2798 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2816 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
2817 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()
2832 if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false, in loadImmediate()
2844 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI); in loadImmediate()
2869 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, in expandLoadImm()
2913 bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO && in loadAndAddSymbolAddress()
2914 SrcReg != Mips::ZERO_64; in loadAndAddSymbolAddress()
2935 bool UseXGOT = STI->getFeatureBits()[Mips::FeatureXGOT] && !IsLocalSym; in loadAndAddSymbolAddress()
2941 if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg && in loadAndAddSymbolAddress()
2948 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc, in loadAndAddSymbolAddress()
2950 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg, in loadAndAddSymbolAddress()
2952 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, DstReg, in loadAndAddSymbolAddress()
2957 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg, in loadAndAddSymbolAddress()
2993 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(CallHiExpr), IDLoc, in loadAndAddSymbolAddress()
2995 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, GPReg, in loadAndAddSymbolAddress()
2997 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg, in loadAndAddSymbolAddress()
3001 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in loadAndAddSymbolAddress()
3007 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3064 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, GPReg, in loadAndAddSymbolAddress()
3068 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in loadAndAddSymbolAddress()
3072 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3111 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3113 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, in loadAndAddSymbolAddress()
3115 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3116 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), in loadAndAddSymbolAddress()
3118 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3119 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3121 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3138 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3140 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3141 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3143 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3145 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
3146 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI); in loadAndAddSymbolAddress()
3148 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3161 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3163 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3165 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3166 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3168 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3169 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3172 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3206 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3207 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3211 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3223 if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg)) in nextReg()
3224 return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1; in nextReg()
3227 case Mips::ZERO: return Mips::AT; in nextReg()
3228 case Mips::AT: return Mips::V0; in nextReg()
3229 case Mips::V0: return Mips::V1; in nextReg()
3230 case Mips::V1: return Mips::A0; in nextReg()
3231 case Mips::A0: return Mips::A1; in nextReg()
3232 case Mips::A1: return Mips::A2; in nextReg()
3233 case Mips::A2: return Mips::A3; in nextReg()
3234 case Mips::A3: return Mips::T0; in nextReg()
3235 case Mips::T0: return Mips::T1; in nextReg()
3236 case Mips::T1: return Mips::T2; in nextReg()
3237 case Mips::T2: return Mips::T3; in nextReg()
3238 case Mips::T3: return Mips::T4; in nextReg()
3239 case Mips::T4: return Mips::T5; in nextReg()
3240 case Mips::T5: return Mips::T6; in nextReg()
3241 case Mips::T6: return Mips::T7; in nextReg()
3242 case Mips::T7: return Mips::S0; in nextReg()
3243 case Mips::S0: return Mips::S1; in nextReg()
3244 case Mips::S1: return Mips::S2; in nextReg()
3245 case Mips::S2: return Mips::S3; in nextReg()
3246 case Mips::S3: return Mips::S4; in nextReg()
3247 case Mips::S4: return Mips::S5; in nextReg()
3248 case Mips::S5: return Mips::S6; in nextReg()
3249 case Mips::S6: return Mips::S7; in nextReg()
3250 case Mips::S7: return Mips::T8; in nextReg()
3251 case Mips::T8: return Mips::T9; in nextReg()
3252 case Mips::T9: return Mips::K0; in nextReg()
3253 case Mips::K0: return Mips::K1; in nextReg()
3254 case Mips::K1: return Mips::GP; in nextReg()
3255 case Mips::GP: return Mips::SP; in nextReg()
3256 case Mips::SP: return Mips::FP; in nextReg()
3257 case Mips::FP: return Mips::RA; in nextReg()
3258 case Mips::RA: return Mips::ZERO; in nextReg()
3259 case Mips::D0: return Mips::F1; in nextReg()
3260 case Mips::D1: return Mips::F3; in nextReg()
3261 case Mips::D2: return Mips::F5; in nextReg()
3262 case Mips::D3: return Mips::F7; in nextReg()
3263 case Mips::D4: return Mips::F9; in nextReg()
3264 case Mips::D5: return Mips::F11; in nextReg()
3265 case Mips::D6: return Mips::F13; in nextReg()
3266 case Mips::D7: return Mips::F15; in nextReg()
3267 case Mips::D8: return Mips::F17; in nextReg()
3268 case Mips::D9: return Mips::F19; in nextReg()
3269 case Mips::D10: return Mips::F21; in nextReg()
3270 case Mips::D11: return Mips::F23; in nextReg()
3271 case Mips::D12: return Mips::F25; in nextReg()
3272 case Mips::D13: return Mips::F27; in nextReg()
3273 case Mips::D14: return Mips::F29; in nextReg()
3274 case Mips::D15: return Mips::F31; in nextReg()
3297 TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr), in emitPartialAddress()
3300 TOut.emitRRX(Mips::LD, ATReg, GPReg, MCOperand::createExpr(GotExpr), in emitPartialAddress()
3316 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in emitPartialAddress()
3327 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in emitPartialAddress()
3329 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, in emitPartialAddress()
3331 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in emitPartialAddress()
3332 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), in emitPartialAddress()
3334 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in emitPartialAddress()
3370 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, in expandLoadSingleImmToGPR()
3389 unsigned TmpReg = Mips::ZERO; in expandLoadSingleImmToFPR()
3397 if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister, in expandLoadSingleImmToFPR()
3400 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3423 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr), in expandLoadSingleImmToFPR()
3443 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, in expandLoadDoubleImmToGPR()
3447 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3451 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3481 TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in expandLoadDoubleImmToGPR()
3485 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
3487 TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
3488 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI); in expandLoadDoubleImmToGPR()
3506 unsigned TmpReg = Mips::ZERO; in expandLoadDoubleImmToFPR()
3516 if (TmpReg != Mips::ZERO && in expandLoadDoubleImmToFPR()
3517 loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc, in expandLoadDoubleImmToFPR()
3520 TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3524 if (TmpReg != Mips::ZERO && in expandLoadDoubleImmToFPR()
3525 loadImmediate(Hi_32(ImmOp64), TmpReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToFPR()
3530 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3531 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3533 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3534 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3560 TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg, in expandLoadDoubleImmToFPR()
3577 Inst.setOpcode(Mips::BEQ_MM); in expandUncondBranchMMPseudo()
3578 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3579 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3587 Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM); in expandUncondBranchMMPseudo()
3594 Inst.setOpcode(Mips::BEQ_MM); in expandUncondBranchMMPseudo()
3595 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3596 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3628 case Mips::BneImm: in expandBranchImm()
3629 OpCode = Mips::BNE; in expandBranchImm()
3631 case Mips::BeqImm: in expandBranchImm()
3632 OpCode = Mips::BEQ; in expandBranchImm()
3634 case Mips::BEQLImmMacro: in expandBranchImm()
3635 OpCode = Mips::BEQL; in expandBranchImm()
3638 case Mips::BNELImmMacro: in expandBranchImm()
3639 OpCode = Mips::BNEL; in expandBranchImm()
3650 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, in expandBranchImm()
3652 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in expandBranchImm()
3654 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, in expandBranchImm()
3663 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true, in expandBranchImm()
3670 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in expandBranchImm()
3699 bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) || in expandMem16Inst()
3700 (DstRegClassID == Mips::GPR64RegClassID); in expandMem16Inst()
3730 if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true, in expandMem16Inst()
3735 if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64) in expandMem16Inst()
3736 TOut.emitRRR(ABI.ArePtrs64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, in expandMem16Inst()
3781 TOut.emitRX(Mips::LUi, TmpReg, HighestOperand, IDLoc, STI); in expandMem16Inst()
3782 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HigherOperand, IDLoc, STI); in expandMem16Inst()
3783 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3784 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HiOperand, IDLoc, STI); in expandMem16Inst()
3785 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3786 if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64) in expandMem16Inst()
3787 TOut.emitRRR(Mips::DADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
3791 TOut.emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI); in expandMem16Inst()
3792 if (BaseReg != Mips::ZERO) in expandMem16Inst()
3793 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
3826 bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) || in expandMem9Inst()
3827 (DstRegClassID == Mips::GPR64RegClassID); in expandMem9Inst()
3867 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; in expandLoadStoreMultiple()
3875 (Inst.getOperand(OpNum - 2).getReg() == Mips::SP || in expandLoadStoreMultiple()
3876 Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) && in expandLoadStoreMultiple()
3877 (Inst.getOperand(OpNum - 3).getReg() == Mips::RA || in expandLoadStoreMultiple()
3878 Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) { in expandLoadStoreMultiple()
3881 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6; in expandLoadStoreMultiple()
3883 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM; in expandLoadStoreMultiple()
3918 case Mips::BLTImmMacro: in expandCondBranches()
3919 PseudoOpcode = Mips::BLT; in expandCondBranches()
3921 case Mips::BLEImmMacro: in expandCondBranches()
3922 PseudoOpcode = Mips::BLE; in expandCondBranches()
3924 case Mips::BGEImmMacro: in expandCondBranches()
3925 PseudoOpcode = Mips::BGE; in expandCondBranches()
3927 case Mips::BGTImmMacro: in expandCondBranches()
3928 PseudoOpcode = Mips::BGT; in expandCondBranches()
3930 case Mips::BLTUImmMacro: in expandCondBranches()
3931 PseudoOpcode = Mips::BLTU; in expandCondBranches()
3933 case Mips::BLEUImmMacro: in expandCondBranches()
3934 PseudoOpcode = Mips::BLEU; in expandCondBranches()
3936 case Mips::BGEUImmMacro: in expandCondBranches()
3937 PseudoOpcode = Mips::BGEU; in expandCondBranches()
3939 case Mips::BGTUImmMacro: in expandCondBranches()
3940 PseudoOpcode = Mips::BGTU; in expandCondBranches()
3942 case Mips::BLTLImmMacro: in expandCondBranches()
3943 PseudoOpcode = Mips::BLTL; in expandCondBranches()
3945 case Mips::BLELImmMacro: in expandCondBranches()
3946 PseudoOpcode = Mips::BLEL; in expandCondBranches()
3948 case Mips::BGELImmMacro: in expandCondBranches()
3949 PseudoOpcode = Mips::BGEL; in expandCondBranches()
3951 case Mips::BGTLImmMacro: in expandCondBranches()
3952 PseudoOpcode = Mips::BGTL; in expandCondBranches()
3954 case Mips::BLTULImmMacro: in expandCondBranches()
3955 PseudoOpcode = Mips::BLTUL; in expandCondBranches()
3957 case Mips::BLEULImmMacro: in expandCondBranches()
3958 PseudoOpcode = Mips::BLEUL; in expandCondBranches()
3960 case Mips::BGEULImmMacro: in expandCondBranches()
3961 PseudoOpcode = Mips::BGEUL; in expandCondBranches()
3963 case Mips::BGTULImmMacro: in expandCondBranches()
3964 PseudoOpcode = Mips::BGTUL; in expandCondBranches()
3968 if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(), in expandCondBranches()
3974 case Mips::BLT: in expandCondBranches()
3975 case Mips::BLTU: in expandCondBranches()
3976 case Mips::BLTL: in expandCondBranches()
3977 case Mips::BLTUL: in expandCondBranches()
3981 ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL)); in expandCondBranches()
3982 IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL)); in expandCondBranches()
3983 ZeroSrcOpcode = Mips::BGTZ; in expandCondBranches()
3984 ZeroTrgOpcode = Mips::BLTZ; in expandCondBranches()
3986 case Mips::BLE: in expandCondBranches()
3987 case Mips::BLEU: in expandCondBranches()
3988 case Mips::BLEL: in expandCondBranches()
3989 case Mips::BLEUL: in expandCondBranches()
3993 ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL)); in expandCondBranches()
3994 IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL)); in expandCondBranches()
3995 ZeroSrcOpcode = Mips::BGEZ; in expandCondBranches()
3996 ZeroTrgOpcode = Mips::BLEZ; in expandCondBranches()
3998 case Mips::BGE: in expandCondBranches()
3999 case Mips::BGEU: in expandCondBranches()
4000 case Mips::BGEL: in expandCondBranches()
4001 case Mips::BGEUL: in expandCondBranches()
4005 ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL)); in expandCondBranches()
4006 IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL)); in expandCondBranches()
4007 ZeroSrcOpcode = Mips::BLEZ; in expandCondBranches()
4008 ZeroTrgOpcode = Mips::BGEZ; in expandCondBranches()
4010 case Mips::BGT: in expandCondBranches()
4011 case Mips::BGTU: in expandCondBranches()
4012 case Mips::BGTL: in expandCondBranches()
4013 case Mips::BGTUL: in expandCondBranches()
4017 ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL)); in expandCondBranches()
4018 IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL)); in expandCondBranches()
4019 ZeroSrcOpcode = Mips::BLTZ; in expandCondBranches()
4020 ZeroTrgOpcode = Mips::BGTZ; in expandCondBranches()
4026 bool IsTrgRegZero = (TrgReg == Mips::ZERO); in expandCondBranches()
4027 bool IsSrcRegZero = (SrcReg == Mips::ZERO); in expandCondBranches()
4032 if (PseudoOpcode == Mips::BLT) { in expandCondBranches()
4033 TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
4037 if (PseudoOpcode == Mips::BLE) { in expandCondBranches()
4038 TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
4043 if (PseudoOpcode == Mips::BGE) { in expandCondBranches()
4044 TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
4049 if (PseudoOpcode == Mips::BGT) { in expandCondBranches()
4050 TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
4054 if (PseudoOpcode == Mips::BGTU) { in expandCondBranches()
4055 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO, in expandCondBranches()
4062 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, in expandCondBranches()
4072 if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) || in expandCondBranches()
4073 (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) { in expandCondBranches()
4080 if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) || in expandCondBranches()
4081 (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) { in expandCondBranches()
4087 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, in expandCondBranches()
4105 TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE, in expandCondBranches()
4106 IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO, in expandCondBranches()
4143 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, in expandCondBranches()
4147 TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL) in expandCondBranches()
4148 : (AcceptsEquality ? Mips::BEQ : Mips::BNE), in expandCondBranches()
4149 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, in expandCondBranches()
4193 DivOp = Signed ? Mips::DSDIV : Mips::DUDIV; in expandDivRem()
4194 ZeroReg = Mips::ZERO_64; in expandDivRem()
4195 SubOp = Mips::DSUB; in expandDivRem()
4197 DivOp = Signed ? Mips::SDIV : Mips::UDIV; in expandDivRem()
4198 ZeroReg = Mips::ZERO; in expandDivRem()
4199 SubOp = Mips::SUB; in expandDivRem()
4205 bool isDiv = Opcode == Mips::SDivMacro || Opcode == Mips::SDivIMacro || in expandDivRem()
4206 Opcode == Mips::UDivMacro || Opcode == Mips::UDivIMacro || in expandDivRem()
4207 Opcode == Mips::DSDivMacro || Opcode == Mips::DSDivIMacro || in expandDivRem()
4208 Opcode == Mips::DUDivMacro || Opcode == Mips::DUDivIMacro; in expandDivRem()
4210 bool isRem = Opcode == Mips::SRemMacro || Opcode == Mips::SRemIMacro || in expandDivRem()
4211 Opcode == Mips::URemMacro || Opcode == Mips::URemIMacro || in expandDivRem()
4212 Opcode == Mips::DSRemMacro || Opcode == Mips::DSRemIMacro || in expandDivRem()
4213 Opcode == Mips::DURemMacro || Opcode == Mips::DURemIMacro; in expandDivRem()
4222 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4224 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4229 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
4232 TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI); in expandDivRem()
4238 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue), in expandDivRem()
4242 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4252 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) { in expandDivRem()
4254 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4257 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4263 if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) { in expandDivRem()
4274 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4279 TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI); in expandDivRem()
4285 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4291 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4302 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem()
4310 TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
4313 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI); in expandDivRem()
4316 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI); in expandDivRem()
4320 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI); in expandDivRem()
4323 TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
4325 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI); in expandDivRem()
4329 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4350 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4351 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4353 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI); in expandTrunc()
4354 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI); in expandTrunc()
4355 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI); in expandTrunc()
4357 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32) in expandTrunc()
4358 : Mips::CVT_W_S, in expandTrunc()
4360 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI); in expandTrunc()
4365 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32) in expandTrunc()
4366 : Mips::TRUNC_W_S, in expandTrunc()
4415 TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg, in expandUlh()
4417 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI); in expandUlh()
4418 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI); in expandUlh()
4419 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUlh()
4460 TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI); in expandUsh()
4461 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4462 TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI); in expandUsh()
4463 TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI); in expandUsh()
4464 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4465 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUsh()
4467 TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI); in expandUsh()
4468 TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI); in expandUsh()
4469 TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI); in expandUsh()
4500 bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw); in expandUxw()
4519 unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL; in expandUxw()
4520 unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR; in expandUxw()
4525 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI); in expandUxw()
4547 case Mips::SGE: in expandSge()
4548 OpCode = Mips::SLT; in expandSge()
4550 case Mips::SGEU: in expandSge()
4551 OpCode = Mips::SLTu; in expandSge()
4559 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSge()
4581 case Mips::SGEImm: in expandSgeImm()
4582 case Mips::SGEImm64: in expandSgeImm()
4583 OpRegCode = Mips::SLT; in expandSgeImm()
4584 OpImmCode = Mips::SLTi; in expandSgeImm()
4586 case Mips::SGEUImm: in expandSgeImm()
4587 case Mips::SGEUImm64: in expandSgeImm()
4588 OpRegCode = Mips::SLTu; in expandSgeImm()
4589 OpImmCode = Mips::SLTiu; in expandSgeImm()
4599 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4609 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSgeImm()
4614 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4638 case Mips::SGTImm: in expandSgtImm()
4639 case Mips::SGTImm64: in expandSgtImm()
4640 OpCode = Mips::SLT; in expandSgtImm()
4642 case Mips::SGTUImm: in expandSgtImm()
4643 case Mips::SGTUImm64: in expandSgtImm()
4644 OpCode = Mips::SLTu; in expandSgtImm()
4657 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSgtImm()
4684 case Mips::SLE: in expandSle()
4685 OpCode = Mips::SLT; in expandSle()
4687 case Mips::SLEU: in expandSle()
4688 OpCode = Mips::SLTu; in expandSle()
4696 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSle()
4718 case Mips::SLEImm: in expandSleImm()
4719 case Mips::SLEImm64: in expandSleImm()
4720 OpRegCode = Mips::SLT; in expandSleImm()
4722 case Mips::SLEUImm: in expandSleImm()
4723 case Mips::SLEUImm64: in expandSleImm()
4724 OpRegCode = Mips::SLTu; in expandSleImm()
4739 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSleImm()
4744 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSleImm()
4759 unsigned ATReg = Mips::NoRegister; in expandAliasImmediate()
4760 unsigned FinalDstReg = Mips::NoRegister; in expandAliasImmediate()
4777 if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, in expandAliasImmediate()
4782 case Mips::ADDi: in expandAliasImmediate()
4783 FinalOpcode = Mips::ADD; in expandAliasImmediate()
4785 case Mips::ADDiu: in expandAliasImmediate()
4786 FinalOpcode = Mips::ADDu; in expandAliasImmediate()
4788 case Mips::ANDi: in expandAliasImmediate()
4789 FinalOpcode = Mips::AND; in expandAliasImmediate()
4791 case Mips::NORImm: in expandAliasImmediate()
4792 FinalOpcode = Mips::NOR; in expandAliasImmediate()
4794 case Mips::ORi: in expandAliasImmediate()
4795 FinalOpcode = Mips::OR; in expandAliasImmediate()
4797 case Mips::SLTi: in expandAliasImmediate()
4798 FinalOpcode = Mips::SLT; in expandAliasImmediate()
4800 case Mips::SLTiu: in expandAliasImmediate()
4801 FinalOpcode = Mips::SLTu; in expandAliasImmediate()
4803 case Mips::XORi: in expandAliasImmediate()
4804 FinalOpcode = Mips::XOR; in expandAliasImmediate()
4806 case Mips::ADDi_MM: in expandAliasImmediate()
4807 FinalOpcode = Mips::ADD_MM; in expandAliasImmediate()
4809 case Mips::ADDiu_MM: in expandAliasImmediate()
4810 FinalOpcode = Mips::ADDu_MM; in expandAliasImmediate()
4812 case Mips::ANDi_MM: in expandAliasImmediate()
4813 FinalOpcode = Mips::AND_MM; in expandAliasImmediate()
4815 case Mips::ORi_MM: in expandAliasImmediate()
4816 FinalOpcode = Mips::OR_MM; in expandAliasImmediate()
4818 case Mips::SLTi_MM: in expandAliasImmediate()
4819 FinalOpcode = Mips::SLT_MM; in expandAliasImmediate()
4821 case Mips::SLTiu_MM: in expandAliasImmediate()
4822 FinalOpcode = Mips::SLTu_MM; in expandAliasImmediate()
4824 case Mips::XORi_MM: in expandAliasImmediate()
4825 FinalOpcode = Mips::XOR_MM; in expandAliasImmediate()
4827 case Mips::ANDi64: in expandAliasImmediate()
4828 FinalOpcode = Mips::AND64; in expandAliasImmediate()
4830 case Mips::NORImm64: in expandAliasImmediate()
4831 FinalOpcode = Mips::NOR64; in expandAliasImmediate()
4833 case Mips::ORi64: in expandAliasImmediate()
4834 FinalOpcode = Mips::OR64; in expandAliasImmediate()
4836 case Mips::SLTImm64: in expandAliasImmediate()
4837 FinalOpcode = Mips::SLT64; in expandAliasImmediate()
4839 case Mips::SLTUImm64: in expandAliasImmediate()
4840 FinalOpcode = Mips::SLTu64; in expandAliasImmediate()
4842 case Mips::XORi64: in expandAliasImmediate()
4843 FinalOpcode = Mips::XOR64; in expandAliasImmediate()
4847 if (FinalDstReg == Mips::NoRegister) in expandAliasImmediate()
4859 unsigned ATReg = Mips::NoRegister; in expandRotation()
4865 unsigned FirstShift = Mips::NOP; in expandRotation()
4866 unsigned SecondShift = Mips::NOP; in expandRotation()
4875 if (Inst.getOpcode() == Mips::ROL) { in expandRotation()
4876 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4877 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4881 if (Inst.getOpcode() == Mips::ROR) { in expandRotation()
4882 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4893 case Mips::ROL: in expandRotation()
4894 FirstShift = Mips::SRLV; in expandRotation()
4895 SecondShift = Mips::SLLV; in expandRotation()
4897 case Mips::ROR: in expandRotation()
4898 FirstShift = Mips::SLLV; in expandRotation()
4899 SecondShift = Mips::SRLV; in expandRotation()
4907 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4910 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4922 unsigned ATReg = Mips::NoRegister; in expandRotationImm()
4927 unsigned FirstShift = Mips::NOP; in expandRotationImm()
4928 unsigned SecondShift = Mips::NOP; in expandRotationImm()
4931 if (Inst.getOpcode() == Mips::ROLImm) { in expandRotationImm()
4936 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
4940 if (Inst.getOpcode() == Mips::RORImm) { in expandRotationImm()
4941 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
4950 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
4957 case Mips::ROLImm: in expandRotationImm()
4958 FirstShift = Mips::SLL; in expandRotationImm()
4959 SecondShift = Mips::SRL; in expandRotationImm()
4961 case Mips::RORImm: in expandRotationImm()
4962 FirstShift = Mips::SRL; in expandRotationImm()
4963 SecondShift = Mips::SLL; in expandRotationImm()
4973 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotationImm()
4984 unsigned ATReg = Mips::NoRegister; in expandDRotation()
4990 unsigned FirstShift = Mips::NOP; in expandDRotation()
4991 unsigned SecondShift = Mips::NOP; in expandDRotation()
5000 if (Inst.getOpcode() == Mips::DROL) { in expandDRotation()
5001 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
5002 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandDRotation()
5006 if (Inst.getOpcode() == Mips::DROR) { in expandDRotation()
5007 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
5018 case Mips::DROL: in expandDRotation()
5019 FirstShift = Mips::DSRLV; in expandDRotation()
5020 SecondShift = Mips::DSLLV; in expandDRotation()
5022 case Mips::DROR: in expandDRotation()
5023 FirstShift = Mips::DSLLV; in expandDRotation()
5024 SecondShift = Mips::DSRLV; in expandDRotation()
5032 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
5035 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandDRotation()
5047 unsigned ATReg = Mips::NoRegister; in expandDRotationImm()
5052 unsigned FirstShift = Mips::NOP; in expandDRotationImm()
5053 unsigned SecondShift = Mips::NOP; in expandDRotationImm()
5058 unsigned FinalOpcode = Mips::NOP; in expandDRotationImm()
5060 FinalOpcode = Mips::DROTR; in expandDRotationImm()
5062 FinalOpcode = Mips::DROTR32; in expandDRotationImm()
5064 if (Inst.getOpcode() == Mips::DROLImm) in expandDRotationImm()
5065 FinalOpcode = Mips::DROTR32; in expandDRotationImm()
5067 FinalOpcode = Mips::DROTR; in expandDRotationImm()
5069 if (Inst.getOpcode() == Mips::DROLImm) in expandDRotationImm()
5070 FinalOpcode = Mips::DROTR; in expandDRotationImm()
5072 FinalOpcode = Mips::DROTR32; in expandDRotationImm()
5076 if (Inst.getOpcode() == Mips::DROLImm) in expandDRotationImm()
5086 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandDRotationImm()
5093 case Mips::DROLImm: in expandDRotationImm()
5095 FirstShift = Mips::DSLL; in expandDRotationImm()
5096 SecondShift = Mips::DSRL32; in expandDRotationImm()
5099 FirstShift = Mips::DSLL32; in expandDRotationImm()
5100 SecondShift = Mips::DSRL32; in expandDRotationImm()
5103 FirstShift = Mips::DSLL32; in expandDRotationImm()
5104 SecondShift = Mips::DSRL; in expandDRotationImm()
5107 case Mips::DRORImm: in expandDRotationImm()
5109 FirstShift = Mips::DSRL; in expandDRotationImm()
5110 SecondShift = Mips::DSLL32; in expandDRotationImm()
5113 FirstShift = Mips::DSRL32; in expandDRotationImm()
5114 SecondShift = Mips::DSLL32; in expandDRotationImm()
5117 FirstShift = Mips::DSRL32; in expandDRotationImm()
5118 SecondShift = Mips::DSLL; in expandDRotationImm()
5130 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandDRotationImm()
5144 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI); in expandAbs()
5146 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI); in expandAbs()
5149 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI); in expandAbs()
5157 unsigned ATReg = Mips::NoRegister; in expandMulImm()
5166 loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, in expandMulImm()
5169 TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT, in expandMulImm()
5172 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulImm()
5180 unsigned ATReg = Mips::NoRegister; in expandMulO()
5189 TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT, in expandMulO()
5192 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5194 TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32, in expandMulO()
5197 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulO()
5200 TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI); in expandMulO()
5207 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI); in expandMulO()
5210 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); in expandMulO()
5214 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5222 unsigned ATReg = Mips::NoRegister; in expandMulOU()
5231 TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu, in expandMulOU()
5234 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulOU()
5235 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulOU()
5237 TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI); in expandMulOU()
5244 TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI); in expandMulOU()
5247 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); in expandMulOU()
5262 TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI); in expandDMULMacro()
5263 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandDMULMacro()
5283 unsigned Opcode = IsLoad ? Mips::LW : Mips::SW; in expandLoadStoreDMacro()
5330 unsigned Opcode = Mips::SWC1; in expandStoreDM1Macro()
5373 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSeq()
5374 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5375 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeq()
5379 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; in expandSeq()
5380 TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI); in expandSeq()
5400 TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI); in expandSeqI()
5404 if (SrcReg == Mips::ZERO) { in expandSeqI()
5406 TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, in expandSeqI()
5414 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu; in expandSeqI()
5416 Opc = Mips::XORi; in expandSeqI()
5424 if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc, in expandSeqI()
5428 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSeqI()
5429 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5434 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5454 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSne()
5455 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSne()
5456 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSne()
5460 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; in expandSne()
5461 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI); in expandSne()
5481 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI); in expandSneI()
5485 if (SrcReg == Mips::ZERO) { in expandSneI()
5487 if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out, in expandSneI()
5496 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu; in expandSneI()
5498 Opc = Mips::XORi; in expandSneI()
5503 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()
5511 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSneI()
5515 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSneI()
5516 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()
5525 case Mips::MFTLO: in getRegisterForMxtrDSP()
5526 case Mips::MTTLO: in getRegisterForMxtrDSP()
5528 case Mips::AC0: in getRegisterForMxtrDSP()
5529 return Mips::ZERO; in getRegisterForMxtrDSP()
5530 case Mips::AC1: in getRegisterForMxtrDSP()
5531 return Mips::A0; in getRegisterForMxtrDSP()
5532 case Mips::AC2: in getRegisterForMxtrDSP()
5533 return Mips::T0; in getRegisterForMxtrDSP()
5534 case Mips::AC3: in getRegisterForMxtrDSP()
5535 return Mips::T4; in getRegisterForMxtrDSP()
5539 case Mips::MFTHI: in getRegisterForMxtrDSP()
5540 case Mips::MTTHI: in getRegisterForMxtrDSP()
5542 case Mips::AC0: in getRegisterForMxtrDSP()
5543 return Mips::AT; in getRegisterForMxtrDSP()
5544 case Mips::AC1: in getRegisterForMxtrDSP()
5545 return Mips::A1; in getRegisterForMxtrDSP()
5546 case Mips::AC2: in getRegisterForMxtrDSP()
5547 return Mips::T1; in getRegisterForMxtrDSP()
5548 case Mips::AC3: in getRegisterForMxtrDSP()
5549 return Mips::T5; in getRegisterForMxtrDSP()
5553 case Mips::MFTACX: in getRegisterForMxtrDSP()
5554 case Mips::MTTACX: in getRegisterForMxtrDSP()
5556 case Mips::AC0: in getRegisterForMxtrDSP()
5557 return Mips::V0; in getRegisterForMxtrDSP()
5558 case Mips::AC1: in getRegisterForMxtrDSP()
5559 return Mips::A2; in getRegisterForMxtrDSP()
5560 case Mips::AC2: in getRegisterForMxtrDSP()
5561 return Mips::T2; in getRegisterForMxtrDSP()
5562 case Mips::AC3: in getRegisterForMxtrDSP()
5563 return Mips::T6; in getRegisterForMxtrDSP()
5567 case Mips::MFTDSP: in getRegisterForMxtrDSP()
5568 case Mips::MTTDSP: in getRegisterForMxtrDSP()
5569 return Mips::S0; in getRegisterForMxtrDSP()
5579 case Mips::F0: return Mips::ZERO; in getRegisterForMxtrFP()
5580 case Mips::F1: return Mips::AT; in getRegisterForMxtrFP()
5581 case Mips::F2: return Mips::V0; in getRegisterForMxtrFP()
5582 case Mips::F3: return Mips::V1; in getRegisterForMxtrFP()
5583 case Mips::F4: return Mips::A0; in getRegisterForMxtrFP()
5584 case Mips::F5: return Mips::A1; in getRegisterForMxtrFP()
5585 case Mips::F6: return Mips::A2; in getRegisterForMxtrFP()
5586 case Mips::F7: return Mips::A3; in getRegisterForMxtrFP()
5587 case Mips::F8: return Mips::T0; in getRegisterForMxtrFP()
5588 case Mips::F9: return Mips::T1; in getRegisterForMxtrFP()
5589 case Mips::F10: return Mips::T2; in getRegisterForMxtrFP()
5590 case Mips::F11: return Mips::T3; in getRegisterForMxtrFP()
5591 case Mips::F12: return Mips::T4; in getRegisterForMxtrFP()
5592 case Mips::F13: return Mips::T5; in getRegisterForMxtrFP()
5593 case Mips::F14: return Mips::T6; in getRegisterForMxtrFP()
5594 case Mips::F15: return Mips::T7; in getRegisterForMxtrFP()
5595 case Mips::F16: return Mips::S0; in getRegisterForMxtrFP()
5596 case Mips::F17: return Mips::S1; in getRegisterForMxtrFP()
5597 case Mips::F18: return Mips::S2; in getRegisterForMxtrFP()
5598 case Mips::F19: return Mips::S3; in getRegisterForMxtrFP()
5599 case Mips::F20: return Mips::S4; in getRegisterForMxtrFP()
5600 case Mips::F21: return Mips::S5; in getRegisterForMxtrFP()
5601 case Mips::F22: return Mips::S6; in getRegisterForMxtrFP()
5602 case Mips::F23: return Mips::S7; in getRegisterForMxtrFP()
5603 case Mips::F24: return Mips::T8; in getRegisterForMxtrFP()
5604 case Mips::F25: return Mips::T9; in getRegisterForMxtrFP()
5605 case Mips::F26: return Mips::K0; in getRegisterForMxtrFP()
5606 case Mips::F27: return Mips::K1; in getRegisterForMxtrFP()
5607 case Mips::F28: return Mips::GP; in getRegisterForMxtrFP()
5608 case Mips::F29: return Mips::SP; in getRegisterForMxtrFP()
5609 case Mips::F30: return Mips::FP; in getRegisterForMxtrFP()
5610 case Mips::F31: return Mips::RA; in getRegisterForMxtrFP()
5618 case Mips::COP00: return Mips::ZERO; in getRegisterForMxtrC0()
5619 case Mips::COP01: return Mips::AT; in getRegisterForMxtrC0()
5620 case Mips::COP02: return Mips::V0; in getRegisterForMxtrC0()
5621 case Mips::COP03: return Mips::V1; in getRegisterForMxtrC0()
5622 case Mips::COP04: return Mips::A0; in getRegisterForMxtrC0()
5623 case Mips::COP05: return Mips::A1; in getRegisterForMxtrC0()
5624 case Mips::COP06: return Mips::A2; in getRegisterForMxtrC0()
5625 case Mips::COP07: return Mips::A3; in getRegisterForMxtrC0()
5626 case Mips::COP08: return Mips::T0; in getRegisterForMxtrC0()
5627 case Mips::COP09: return Mips::T1; in getRegisterForMxtrC0()
5628 case Mips::COP010: return Mips::T2; in getRegisterForMxtrC0()
5629 case Mips::COP011: return Mips::T3; in getRegisterForMxtrC0()
5630 case Mips::COP012: return Mips::T4; in getRegisterForMxtrC0()
5631 case Mips::COP013: return Mips::T5; in getRegisterForMxtrC0()
5632 case Mips::COP014: return Mips::T6; in getRegisterForMxtrC0()
5633 case Mips::COP015: return Mips::T7; in getRegisterForMxtrC0()
5634 case Mips::COP016: return Mips::S0; in getRegisterForMxtrC0()
5635 case Mips::COP017: return Mips::S1; in getRegisterForMxtrC0()
5636 case Mips::COP018: return Mips::S2; in getRegisterForMxtrC0()
5637 case Mips::COP019: return Mips::S3; in getRegisterForMxtrC0()
5638 case Mips::COP020: return Mips::S4; in getRegisterForMxtrC0()
5639 case Mips::COP021: return Mips::S5; in getRegisterForMxtrC0()
5640 case Mips::COP022: return Mips::S6; in getRegisterForMxtrC0()
5641 case Mips::COP023: return Mips::S7; in getRegisterForMxtrC0()
5642 case Mips::COP024: return Mips::T8; in getRegisterForMxtrC0()
5643 case Mips::COP025: return Mips::T9; in getRegisterForMxtrC0()
5644 case Mips::COP026: return Mips::K0; in getRegisterForMxtrC0()
5645 case Mips::COP027: return Mips::K1; in getRegisterForMxtrC0()
5646 case Mips::COP028: return Mips::GP; in getRegisterForMxtrC0()
5647 case Mips::COP029: return Mips::SP; in getRegisterForMxtrC0()
5648 case Mips::COP030: return Mips::FP; in getRegisterForMxtrC0()
5649 case Mips::COP031: return Mips::RA; in getRegisterForMxtrC0()
5665 case Mips::MFTC0: in expandMXTRAlias()
5668 case Mips::MTTC0: in expandMXTRAlias()
5673 case Mips::MFTGPR: in expandMXTRAlias()
5676 case Mips::MTTGPR: in expandMXTRAlias()
5679 case Mips::MFTLO: in expandMXTRAlias()
5680 case Mips::MFTHI: in expandMXTRAlias()
5681 case Mips::MFTACX: in expandMXTRAlias()
5682 case Mips::MFTDSP: in expandMXTRAlias()
5685 case Mips::MTTLO: in expandMXTRAlias()
5686 case Mips::MTTHI: in expandMXTRAlias()
5687 case Mips::MTTACX: in expandMXTRAlias()
5688 case Mips::MTTDSP: in expandMXTRAlias()
5692 case Mips::MFTHC1: in expandMXTRAlias()
5695 case Mips::MFTC1: in expandMXTRAlias()
5700 case Mips::MTTHC1: in expandMXTRAlias()
5703 case Mips::MTTC1: in expandMXTRAlias()
5707 case Mips::CFTC1: in expandMXTRAlias()
5710 case Mips::CTTC1: in expandMXTRAlias()
5718 : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg() in expandMXTRAlias()
5721 TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc, in expandMXTRAlias()
5735 unsigned Opcode = Inst.getOpcode() == Mips::SaaAddr ? Mips::SAA : Mips::SAAD; in expandSaaAddr()
5765 case Mips::DATI: in checkEarlyTargetMatchPredicate()
5766 case Mips::DAHI: in checkEarlyTargetMatchPredicate()
5778 case Mips::DAUI: in checkTargetMatchPredicate()
5779 if (Inst.getOperand(1).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5780 Inst.getOperand(1).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5787 case Mips::JALR_HB: in checkTargetMatchPredicate()
5788 case Mips::JALR_HB64: in checkTargetMatchPredicate()
5789 case Mips::JALRC_HB_MMR6: in checkTargetMatchPredicate()
5790 case Mips::JALRC_MMR6: in checkTargetMatchPredicate()
5794 case Mips::LWP_MM: in checkTargetMatchPredicate()
5798 case Mips::SYNC: in checkTargetMatchPredicate()
5802 case Mips::MFC0: in checkTargetMatchPredicate()
5803 case Mips::MTC0: in checkTargetMatchPredicate()
5804 case Mips::MTC2: in checkTargetMatchPredicate()
5805 case Mips::MFC2: in checkTargetMatchPredicate()
5821 case Mips::BLEZC: case Mips::BLEZC_MMR6: in checkTargetMatchPredicate()
5822 case Mips::BGEZC: case Mips::BGEZC_MMR6: in checkTargetMatchPredicate()
5823 case Mips::BGTZC: case Mips::BGTZC_MMR6: in checkTargetMatchPredicate()
5824 case Mips::BLTZC: case Mips::BLTZC_MMR6: in checkTargetMatchPredicate()
5825 case Mips::BEQZC: case Mips::BEQZC_MMR6: in checkTargetMatchPredicate()
5826 case Mips::BNEZC: case Mips::BNEZC_MMR6: in checkTargetMatchPredicate()
5827 case Mips::BLEZC64: in checkTargetMatchPredicate()
5828 case Mips::BGEZC64: in checkTargetMatchPredicate()
5829 case Mips::BGTZC64: in checkTargetMatchPredicate()
5830 case Mips::BLTZC64: in checkTargetMatchPredicate()
5831 case Mips::BEQZC64: in checkTargetMatchPredicate()
5832 case Mips::BNEZC64: in checkTargetMatchPredicate()
5833 if (Inst.getOperand(0).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5834 Inst.getOperand(0).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5837 case Mips::BGEC: case Mips::BGEC_MMR6: in checkTargetMatchPredicate()
5838 case Mips::BLTC: case Mips::BLTC_MMR6: in checkTargetMatchPredicate()
5839 case Mips::BGEUC: case Mips::BGEUC_MMR6: in checkTargetMatchPredicate()
5840 case Mips::BLTUC: case Mips::BLTUC_MMR6: in checkTargetMatchPredicate()
5841 case Mips::BEQC: case Mips::BEQC_MMR6: in checkTargetMatchPredicate()
5842 case Mips::BNEC: case Mips::BNEC_MMR6: in checkTargetMatchPredicate()
5843 case Mips::BGEC64: in checkTargetMatchPredicate()
5844 case Mips::BLTC64: in checkTargetMatchPredicate()
5845 case Mips::BGEUC64: in checkTargetMatchPredicate()
5846 case Mips::BLTUC64: in checkTargetMatchPredicate()
5847 case Mips::BEQC64: in checkTargetMatchPredicate()
5848 case Mips::BNEC64: in checkTargetMatchPredicate()
5849 if (Inst.getOperand(0).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5850 Inst.getOperand(0).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5852 if (Inst.getOperand(1).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5853 Inst.getOperand(1).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5858 case Mips::DINS: { in checkTargetMatchPredicate()
5867 case Mips::DINSM: in checkTargetMatchPredicate()
5868 case Mips::DINSU: { in checkTargetMatchPredicate()
5877 case Mips::DEXT: { in checkTargetMatchPredicate()
5886 case Mips::DEXTM: in checkTargetMatchPredicate()
5887 case Mips::DEXTU: { in checkTargetMatchPredicate()
5896 case Mips::CRC32B: case Mips::CRC32CB: in checkTargetMatchPredicate()
5897 case Mips::CRC32H: case Mips::CRC32CH: in checkTargetMatchPredicate()
5898 case Mips::CRC32W: case Mips::CRC32CW: in checkTargetMatchPredicate()
5899 case Mips::CRC32D: case Mips::CRC32CD: in checkTargetMatchPredicate()
5907 (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters()) in checkTargetMatchPredicate()
6138 (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) && in ConvertXWPOperands()
6326 (isGP64bit()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, ATIndex); in getATReg()
6793 unsigned PrevReg = Mips::NoRegister; in parseRegisterList()
6808 if ((isGP64bit() && RegNo == Mips::RA_64) || in parseRegisterList()
6809 (!isGP64bit() && RegNo == Mips::RA)) { in parseRegisterList()
6814 if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) || in parseRegisterList()
6815 (((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) && in parseRegisterList()
6828 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()
6829 ((isGP64bit() && (RegNo != Mips::S0_64) && (RegNo != Mips::RA_64)) || in parseRegisterList()
6830 (!isGP64bit() && (RegNo != Mips::S0) && (RegNo != Mips::RA)))) { in parseRegisterList()
6833 } else if (!(((RegNo == Mips::FP || RegNo == Mips::RA || in parseRegisterList()
6834 (RegNo >= Mips::S0 && RegNo <= Mips::S7)) && in parseRegisterList()
6836 ((RegNo == Mips::FP_64 || RegNo == Mips::RA_64 || in parseRegisterList()
6837 (RegNo >= Mips::S0_64 && RegNo <= Mips::S7_64)) && in parseRegisterList()
6841 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()
6842 ((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) || in parseRegisterList()
6843 (RegNo != Mips::FP_64 && RegNo != Mips::RA_64 && in parseRegisterList()
7145 setFeatureBits(Mips::FeatureMSA, "msa"); in parseSetMsaDirective()
7158 clearFeatureBits(Mips::FeatureMSA, "msa"); in parseSetNoMsaDirective()
7173 clearFeatureBits(Mips::FeatureDSP, "dsp"); in parseSetNoDspDirective()
7188 clearFeatureBits(Mips::FeatureMips3D, "mips3d"); in parseSetNoMips3DDirective()
7203 setFeatureBits(Mips::FeatureMips16, "mips16"); in parseSetMips16Directive()
7219 clearFeatureBits(Mips::FeatureMips16, "mips16"); in parseSetNoMips16Directive()
7261 clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseSetOddSPRegDirective()
7275 setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseSetNoOddSPRegDirective()
7290 setFeatureBits(Mips::FeatureMT, "mt"); in parseSetMtDirective()
7306 clearFeatureBits(Mips::FeatureMT, "mt"); in parseSetNoMtDirective()
7323 clearFeatureBits(Mips::FeatureCRC, "crc"); in parseSetNoCRCDirective()
7340 clearFeatureBits(Mips::FeatureVirt, "virt"); in parseSetNoVirtDirective()
7357 clearFeatureBits(Mips::FeatureGINV, "ginv"); in parseSetNoGINVDirective()
7407 setFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseSetSoftFloatDirective()
7418 clearFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseSetHardFloatDirective()
7525 case Mips::FeatureMips3D: in parseSetFeature()
7526 setFeatureBits(Mips::FeatureMips3D, "mips3d"); in parseSetFeature()
7529 case Mips::FeatureDSP: in parseSetFeature()
7530 setFeatureBits(Mips::FeatureDSP, "dsp"); in parseSetFeature()
7533 case Mips::FeatureDSPR2: in parseSetFeature()
7534 setFeatureBits(Mips::FeatureDSPR2, "dspr2"); in parseSetFeature()
7537 case Mips::FeatureMicroMips: in parseSetFeature()
7538 setFeatureBits(Mips::FeatureMicroMips, "micromips"); in parseSetFeature()
7541 case Mips::FeatureMips1: in parseSetFeature()
7545 case Mips::FeatureMips2: in parseSetFeature()
7549 case Mips::FeatureMips3: in parseSetFeature()
7553 case Mips::FeatureMips4: in parseSetFeature()
7557 case Mips::FeatureMips5: in parseSetFeature()
7561 case Mips::FeatureMips32: in parseSetFeature()
7565 case Mips::FeatureMips32r2: in parseSetFeature()
7569 case Mips::FeatureMips32r3: in parseSetFeature()
7573 case Mips::FeatureMips32r5: in parseSetFeature()
7577 case Mips::FeatureMips32r6: in parseSetFeature()
7581 case Mips::FeatureMips64: in parseSetFeature()
7585 case Mips::FeatureMips64r2: in parseSetFeature()
7589 case Mips::FeatureMips64r3: in parseSetFeature()
7593 case Mips::FeatureMips64r5: in parseSetFeature()
7597 case Mips::FeatureMips64r6: in parseSetFeature()
7601 case Mips::FeatureCRC: in parseSetFeature()
7602 setFeatureBits(Mips::FeatureCRC, "crc"); in parseSetFeature()
7605 case Mips::FeatureVirt: in parseSetFeature()
7606 setFeatureBits(Mips::FeatureVirt, "virt"); in parseSetFeature()
7609 case Mips::FeatureGINV: in parseSetFeature()
7610 setFeatureBits(Mips::FeatureGINV, "ginv"); in parseSetFeature()
7914 clearFeatureBits(Mips::FeatureMicroMips, "micromips"); in parseDirectiveSet()
7924 return parseSetFeature(Mips::FeatureMicroMips); in parseDirectiveSet()
7929 return parseSetFeature(Mips::FeatureMips1); in parseDirectiveSet()
7931 return parseSetFeature(Mips::FeatureMips2); in parseDirectiveSet()
7933 return parseSetFeature(Mips::FeatureMips3); in parseDirectiveSet()
7935 return parseSetFeature(Mips::FeatureMips4); in parseDirectiveSet()
7937 return parseSetFeature(Mips::FeatureMips5); in parseDirectiveSet()
7939 return parseSetFeature(Mips::FeatureMips32); in parseDirectiveSet()
7941 return parseSetFeature(Mips::FeatureMips32r2); in parseDirectiveSet()
7943 return parseSetFeature(Mips::FeatureMips32r3); in parseDirectiveSet()
7945 return parseSetFeature(Mips::FeatureMips32r5); in parseDirectiveSet()
7947 return parseSetFeature(Mips::FeatureMips32r6); in parseDirectiveSet()
7949 return parseSetFeature(Mips::FeatureMips64); in parseDirectiveSet()
7951 return parseSetFeature(Mips::FeatureMips64r2); in parseDirectiveSet()
7953 return parseSetFeature(Mips::FeatureMips64r3); in parseDirectiveSet()
7955 return parseSetFeature(Mips::FeatureMips64r5); in parseDirectiveSet()
7961 return parseSetFeature(Mips::FeatureMips64r6); in parseDirectiveSet()
7964 return parseSetFeature(Mips::FeatureDSP); in parseDirectiveSet()
7966 return parseSetFeature(Mips::FeatureDSPR2); in parseDirectiveSet()
7970 return parseSetFeature(Mips::FeatureMips3D); in parseDirectiveSet()
7986 return parseSetFeature(Mips::FeatureCRC); in parseDirectiveSet()
7990 return parseSetFeature(Mips::FeatureVirt); in parseDirectiveSet()
7994 return parseSetFeature(Mips::FeatureGINV); in parseDirectiveSet()
8238 clearModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseDirectiveModule()
8261 setModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseDirectiveModule()
8282 setModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseDirectiveModule()
8301 clearModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseDirectiveModule()
8320 setModuleFeatureBits(Mips::FeatureMT, "mt"); in parseDirectiveModule()
8339 setModuleFeatureBits(Mips::FeatureCRC, "crc"); in parseDirectiveModule()
8358 clearModuleFeatureBits(Mips::FeatureCRC, "crc"); in parseDirectiveModule()
8377 setModuleFeatureBits(Mips::FeatureVirt, "virt"); in parseDirectiveModule()
8396 clearModuleFeatureBits(Mips::FeatureVirt, "virt"); in parseDirectiveModule()
8415 setModuleFeatureBits(Mips::FeatureGINV, "ginv"); in parseDirectiveModule()
8434 clearModuleFeatureBits(Mips::FeatureGINV, "ginv"); in parseDirectiveModule()
8515 setModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8516 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
8518 setFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8519 clearFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
8541 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8542 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
8544 clearFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8545 clearFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
8550 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8551 setModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
8553 clearFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
8554 setFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()