Lines Matching refs:bits
38 bits<10> offset;
40 bits<16> Inst;
46 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> {
47 bits<3> rs;
48 bits<7> offset;
50 bits<16> Inst;
57 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
58 bits<5> rs;
60 bits<16> Inst;
68 bits<5> rt;
69 bits<5> rs;
70 bits<16> offset;
72 bits<32> Inst;
81 bits<5> rt;
82 bits<5> rs;
83 bits<16> offset;
85 bits<32> Inst;
93 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
94 bits<5> imm;
96 bits<16> Inst;
103 class POOL16C_LWM_SWM_FM_MM16R6<bits<4> funct> {
104 bits<2> rt;
105 bits<4> addr;
107 bits<16> Inst;
115 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
116 bits<5> rd;
117 bits<5> rt;
119 bits<32> Inst;
129 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
130 bits<21> addr;
131 bits<5> hint;
133 bits<32> Inst;
142 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
143 bits<5> rd;
144 bits<5> rt;
145 bits<5> rs;
147 bits<32> Inst;
157 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
158 bits<5> rt;
159 bits<5> rs;
160 bits<16> imm16;
162 bits<32> Inst;
171 bits<21> addr;
172 bits<5> rt;
173 bits<5> base = addr{20-16};
174 bits<16> offset = addr{15-0};
176 bits<32> Inst;
185 bits<21> addr;
186 bits<5> rt;
187 bits<5> base = addr{20-16};
188 bits<16> offset = addr{15-0};
190 bits<32> Inst;
198 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
199 bits<5> rt;
200 bits<19> imm;
202 bits<32> Inst;
210 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
211 bits<5> rt;
212 bits<16> imm;
214 bits<32> Inst;
222 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
223 bits<5> rd;
224 bits<5> rs;
225 bits<5> rt;
227 bits<32> Inst;
237 class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op>
239 bits<32> Inst;
249 class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> {
250 bits<5> rt;
251 bits<5> rd;
252 bits<32> Inst;
262 bits<5> rt;
263 bits<5> rs;
264 bits<3> sel;
265 bits<32> Inst;
277 bits<5> stype;
279 bits<32> Inst;
289 bits<21> addr;
290 bits<5> base = addr{20-16};
291 bits<16> immediate = addr{15-0};
293 bits<32> Inst;
301 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
302 bits<5> rs;
303 bits<5> rt;
305 bits<32> Inst;
314 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
315 bits<5> rs;
316 bits<5> rt;
318 bits<32> Inst;
328 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
329 bits<5> rd;
330 bits<5> rs;
331 bits<5> rt;
332 bits<2> bp;
334 bits<32> Inst;
346 bits<5> rs;
347 bits<5> rt;
348 bits<16> imm;
350 bits<32> Inst;
358 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
359 bits<5> rd;
360 bits<5> rs;
361 bits<5> rt;
362 bits<2> imm2;
364 bits<32> Inst;
375 class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
376 bits<5> rt;
377 bits<21> addr;
378 bits<5> base = addr{20-16};
379 bits<16> offset = addr{15-0};
381 bits<32> Inst;
390 bits<5> rt;
391 bits<21> addr;
392 bits<5> base = addr{20-16};
393 bits<16> offset = addr{15-0};
395 bits<32> Inst;
404 bits<5> rt;
405 bits<16> imm16;
407 bits<32> Inst;
415 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
417 bits<5> rt;
418 bits<16> offset;
420 bits<32> Inst;
428 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
430 bits<5> rt;
431 bits<16> offset;
433 bits<32> Inst;
441 class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct>
443 bits<5> rt;
444 bits<5> rs;
446 bits<32> Inst;
455 class POOL32A_EXT_INS_FM_MMR6<string instr_asm, bits<6> funct>
457 bits<5> rt;
458 bits<5> rs;
459 bits<5> size;
460 bits<5> pos;
462 bits<32> Inst;
472 class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>
474 bits<32> Inst;
483 bits<32> Inst;
493 bits<10> code_1;
494 bits<10> code_2;
495 bits<32> Inst;
502 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
503 bits<32> Inst;
513 class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>
515 bits<32> Inst;
516 bits<5> rt; // Actually rs but we're sharing code with the standard encodings
526 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate>
528 bits<5> rd;
529 bits<5> rt;
530 bits<5> shamt;
532 bits<32> Inst;
542 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
543 bits<5> rt;
544 bits<21> addr;
546 bits<32> Inst;
554 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
556 bits<5> ft;
557 bits<5> fs;
558 bits<5> fd;
560 bits<32> Inst;
571 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
573 bits<5> ft;
574 bits<5> fs;
575 bits<5> fd;
577 bits<32> Inst;
587 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
589 bits<5> ft;
590 bits<5> fs;
592 bits<32> Inst;
603 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
605 bits<5> ft;
606 bits<5> fs;
607 bits<5> fd;
609 bits<32> Inst;
619 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
621 bits<5> ft;
622 bits<5> fs;
623 bits<5> fd;
625 bits<32> Inst;
635 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
637 bits<5> ft;
638 bits<5> fs;
640 bits<32> Inst;
650 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
652 bits<5> ft;
653 bits<5> fs;
655 bits<32> Inst;
665 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
667 bits<5> ft;
668 bits<5> fs;
670 bits<32> Inst;
681 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
683 bits<5> ft;
684 bits<5> fs;
686 bits<32> Inst;
698 bits<3> rs;
699 bits<3> rt;
700 bits<3> rd;
702 bits<16> Inst;
712 bits<3> rt;
713 bits<3> rs;
715 bits<16> Inst;
724 bits<3> rt;
725 bits<3> rs;
727 bits<16> Inst;
736 bits<3> dst_regs;
737 bits<3> rt;
738 bits<3> rs;
740 bits<16> Inst;
750 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
751 bits<3> rt;
752 bits<3> rs;
754 bits<16> Inst;
762 class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
763 bits<4> code_;
764 bits<16> Inst;
772 bits<3> rs;
773 bits<3> rt;
774 bits<3> rd;
776 bits<16> Inst;
785 class POOL32A_WRPGPR_WSBH_FM_MMR6<string instr_asm, bits<10> funct>
787 bits<5> rt;
788 bits<5> rs;
790 bits<32> Inst;
799 class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
801 bits<5> ft;
802 bits<5> fs;
804 bits<32> Inst;
815 class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt> : MMR6Arch<instr_asm>,
817 bits<5> fs;
818 bits<5> fd;
820 bits<32> Inst;
830 class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
832 bits<5> ft;
833 bits<5> fs;
834 bits<5> fd;
836 bits<32> Inst;
846 class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
848 bits<5> fs;
849 bits<5> fd;
851 bits<32> Inst;
861 class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct>
863 bits<32> Inst;
871 class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode>
873 bits<5> rt;
874 bits<5> rs;
875 bits<3> sel;
877 bits<32> Inst;
888 class POOL32A_GINV_FM_MMR6<string instr_asm, bits<2> ginv>
890 bits<5> rs;
891 bits<2> type;
893 bits<32> Inst;
905 class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct>
907 bits<5> rt;
908 bits<5> fs;
910 bits<32> Inst;
920 class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct>
922 bits<5> rt;
923 bits<5> impl;
925 bits<32> Inst;
934 class CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct>
936 bits<5> rt;
937 bits<5> rs;
938 bits<16> offset;
940 bits<32> Inst;
948 class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct>
950 bits<5> rs;
952 bits<32> Inst;
961 class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {
962 bits<5> rs;
963 bits<21> offset;
965 bits<32> Inst;
972 class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct>
974 bits<5> rt;
975 bits<16> offset;
977 bits<32> Inst;
985 class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct>
987 bits<5> ft;
988 bits<21> addr;
989 bits<5> base = addr{20-16};
990 bits<16> offset = addr{15-0};
992 bits<32> Inst;
1000 class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
1002 bits<5> rt;
1003 bits<21> addr;
1004 bits<5> base = addr{20-16};
1005 bits<11> offset = addr{10-0};
1007 bits<32> Inst;
1017 class POOL32C_LL_E_SC_E_FM_MMR6<string instr_asm, bits<4> majorFunc,
1018 bits<3> minorFunc> : MMR6Arch<instr_asm>,
1020 bits<5> rt;
1021 bits<21> addr;
1022 bits<5> base = addr{20-16};
1023 bits<9> offset = addr{8-0};
1025 bits<32> Inst;