43     : MipsInstrInfo(STI, Mips::Bimm16) {}  in Mips16InstrInfo()
75   if (Mips::CPU16RegsRegClass.contains(DestReg) &&  in copyPhysReg()
76       Mips::GPR32RegClass.contains(SrcReg))  in copyPhysReg()
77     Opc = Mips::MoveR3216;  in copyPhysReg()
78   else if (Mips::GPR32RegClass.contains(DestReg) &&  in copyPhysReg()
79            Mips::CPU16RegsRegClass.contains(SrcReg))  in copyPhysReg()
80     Opc = Mips::Move32R16;  in copyPhysReg()
81   else if ((SrcReg == Mips::HI0) &&  in copyPhysReg()
82            (Mips::CPU16RegsRegClass.contains(DestReg)))  in copyPhysReg()
83     Opc = Mips::Mfhi16, SrcReg = 0;  in copyPhysReg()
84   else if ((SrcReg == Mips::LO0) &&  in copyPhysReg()
85            (Mips::CPU16RegsRegClass.contains(DestReg)))  in copyPhysReg()
86     Opc = Mips::Mflo16, SrcReg = 0;  in copyPhysReg()
116   if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))  in storeRegToStack()
117     Opc = Mips::SwRxSpImmX16;  in storeRegToStack()
135   if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))  in loadRegFromStack()
136     Opc = Mips::LwRxSpImmX16;  in loadRegFromStack()
147   case Mips::RetRA16:  in expandPostRAPseudo()
148     ExpandRetRA16(MBB, MI, Mips::JrcRa16);  in expandPostRAPseudo()
160   case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;  in getOppositeBranchOpc()
161   case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;  in getOppositeBranchOpc()
162   case Mips::BeqzRxImm16: return Mips::BnezRxImm16;  in getOppositeBranchOpc()
163   case Mips::BnezRxImm16: return Mips::BeqzRxImm16;  in getOppositeBranchOpc()
164   case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;  in getOppositeBranchOpc()
165   case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;  in getOppositeBranchOpc()
166   case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;  in getOppositeBranchOpc()
167   case Mips::Btnez16: return Mips::Bteqz16;  in getOppositeBranchOpc()
168   case Mips::BtnezX16: return Mips::BteqzX16;  in getOppositeBranchOpc()
169   case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;  in getOppositeBranchOpc()
170   case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;  in getOppositeBranchOpc()
171   case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;  in getOppositeBranchOpc()
172   case Mips::Bteqz16: return Mips::Btnez16;  in getOppositeBranchOpc()
173   case Mips::BteqzX16: return Mips::BtnezX16;  in getOppositeBranchOpc()
174   case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;  in getOppositeBranchOpc()
175   case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;  in getOppositeBranchOpc()
176   case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;  in getOppositeBranchOpc()
177   case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;  in getOppositeBranchOpc()
178   case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;  in getOppositeBranchOpc()
179   case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;  in getOppositeBranchOpc()
195     case Mips::RA:  in addSaveRestoreRegs()
196     case Mips::S0:  in addSaveRestoreRegs()
197     case Mips::S1:  in addSaveRestoreRegs()
200     case Mips::S2:  in addSaveRestoreRegs()
217   bool SaveS2 = Reserved[Mips::S2];  in makeFrame()
219   unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;  in makeFrame()
224     MIB.addReg(Mips::S2);  in makeFrame()
235       adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);  in makeFrame()
247   bool SaveS2 = Reserved[Mips::S2];  in restoreFrame()
250     Mips::Restore16:Mips::RestoreX16;  in restoreFrame()
261       adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);  in restoreFrame()
267     MIB.addReg(Mips::S2, RegState::Define);  in restoreFrame()
287   MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);  in adjustStackPtrBig()
289   MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);  in adjustStackPtrBig()
290   MIB2.addReg(Mips::SP, RegState::Kill);  in adjustStackPtrBig()
291   MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);  in adjustStackPtrBig()
294   MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),  in adjustStackPtrBig()
295                                                      Mips::SP);  in adjustStackPtrBig()
352       (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);  in loadImmediate()
378   BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);  in loadImmediate()
394       FirstRegSavedTo = Mips::T0;  in loadImmediate()
400   BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);  in loadImmediate()
402   if (FrameReg == Mips::SP) {  in loadImmediate()
409         SecondRegSavedTo = Mips::T1;  in loadImmediate()
416     copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);  in loadImmediate()
417     BuildMI(MBB, II, DL, get(Mips::AdduRxRyRz16), Reg)  in loadImmediate()
422     BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(FrameReg)  in loadImmediate()
435   return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||  in getAnalyzableBrOpc()
436           Opc == Mips::Bimm16  ||  in getAnalyzableBrOpc()
437           Opc == Mips::Bteqz16        || Opc == Mips::Btnez16 ||  in getAnalyzableBrOpc()
438           Opc == Mips::BeqzRxImm16    || Opc == Mips::BnezRxImm16   ||  in getAnalyzableBrOpc()
439           Opc == Mips::BnezRxImmX16   || Opc == Mips::BteqzX16 ||  in getAnalyzableBrOpc()
440           Opc == Mips::BteqzT8CmpX16  || Opc == Mips::BteqzT8CmpiX16 ||  in getAnalyzableBrOpc()
441           Opc == Mips::BteqzT8SltX16  || Opc == Mips::BteqzT8SltuX16  ||  in getAnalyzableBrOpc()
442           Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||  in getAnalyzableBrOpc()
443           Opc == Mips::BtnezX16       || Opc == Mips::BtnezT8CmpX16 ||  in getAnalyzableBrOpc()
444           Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||  in getAnalyzableBrOpc()
445           Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||  in getAnalyzableBrOpc()
446           Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;  in getAnalyzableBrOpc()
457     return get(Mips::AddiuSpImm16);  in AddiuSpImm()
459     return get(Mips::AddiuSpImmX16);  in AddiuSpImm()
475   case Mips::LbRxRyOffMemX16:  in validImmediate()
476   case Mips::LbuRxRyOffMemX16:  in validImmediate()
477   case Mips::LhRxRyOffMemX16:  in validImmediate()
478   case Mips::LhuRxRyOffMemX16:  in validImmediate()
479   case Mips::SbRxRyOffMemX16:  in validImmediate()
480   case Mips::ShRxRyOffMemX16:  in validImmediate()
481   case Mips::LwRxRyOffMemX16:  in validImmediate()
482   case Mips::SwRxRyOffMemX16:  in validImmediate()
483   case Mips::SwRxSpImmX16:  in validImmediate()
484   case Mips::LwRxSpImmX16:  in validImmediate()
486   case Mips::AddiuRxRyOffMemX16:  in validImmediate()
487     if ((Reg == Mips::PC) || (Reg == Mips::SP))  in validImmediate()