Lines Matching refs:IdxVal

5810 static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,  in extractSubVector()  argument
5824 IdxVal &= ~(ElemsPerChunk - 1); in extractSubVector()
5829 Vec->ops().slice(IdxVal, ElemsPerChunk)); in extractSubVector()
5831 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl); in extractSubVector()
5841 static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal, in extract128BitVector() argument
5845 return extractSubVector(Vec, IdxVal, DAG, dl, 128); in extract128BitVector()
5849 static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal, in extract256BitVector() argument
5852 return extractSubVector(Vec, IdxVal, DAG, dl, 256); in extract256BitVector()
5855 static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal, in insertSubVector() argument
5873 IdxVal &= ~(ElemsPerChunk - 1); in insertSubVector()
5875 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl); in insertSubVector()
5885 static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal, in insert128BitVector() argument
5888 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 128); in insert128BitVector()
6082 unsigned IdxVal = Op.getConstantOperandVal(2); in insert1BitVector() local
6088 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal in insert1BitVector()
6102 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(Vec.getNode())) { in insert1BitVector()
6112 assert(IdxVal + SubVecNumElems <= NumElems && in insert1BitVector()
6113 IdxVal % SubVecVT.getSizeInBits() == 0 && in insert1BitVector()
6118 if (IdxVal == 0) { in insert1BitVector()
6137 assert(IdxVal != 0 && "Unexpected index"); in insert1BitVector()
6139 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in insert1BitVector()
6144 assert(IdxVal != 0 && "Unexpected index"); in insert1BitVector()
6147 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal; in insert1BitVector()
6157 if (IdxVal + SubVecNumElems == NumElems) { in insert1BitVector()
6159 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in insert1BitVector()
6172 SDValue ShiftBits = DAG.getTargetConstant(NumElems - IdxVal, dl, MVT::i8); in insert1BitVector()
6188 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal; in insert1BitVector()
6192 APInt Mask0 = APInt::getBitsSet(NumElems, IdxVal, IdxVal + SubVecNumElems); in insert1BitVector()
6214 unsigned LowShift = NumElems - IdxVal; in insert1BitVector()
6221 unsigned HighShift = IdxVal + SubVecNumElems; in insert1BitVector()
18437 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); in LowerEXTRACT_VECTOR_ELT_SSE4() local
18439 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in LowerEXTRACT_VECTOR_ELT_SSE4()
18494 unsigned IdxVal = IdxC->getZExtValue(); in ExtractBitFromMaskVector() local
18495 if (IdxVal == 0) // the operation is legal in ExtractBitFromMaskVector()
18510 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in ExtractBitFromMaskVector()
18562 unsigned IdxVal = IdxC->getZExtValue(); in LowerEXTRACT_VECTOR_ELT() local
18568 Vec = extract128BitVector(Vec, IdxVal, DAG, dl); in LowerEXTRACT_VECTOR_ELT()
18576 IdxVal &= ElemsPerChunk - 1; in LowerEXTRACT_VECTOR_ELT()
18578 DAG.getIntPtrConstant(IdxVal, dl)); in LowerEXTRACT_VECTOR_ELT()
18588 if (IdxVal == 0 && !MayFoldIntoZeroExtend(Op) && in LowerEXTRACT_VECTOR_ELT()
18595 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in LowerEXTRACT_VECTOR_ELT()
18608 int DWordIdx = IdxVal / 4; in LowerEXTRACT_VECTOR_ELT()
18613 int ShiftVal = (IdxVal % 4) * 8; in LowerEXTRACT_VECTOR_ELT()
18620 int WordIdx = IdxVal / 2; in LowerEXTRACT_VECTOR_ELT()
18624 int ShiftVal = (IdxVal % 2) * 8; in LowerEXTRACT_VECTOR_ELT()
18632 if (IdxVal == 0) in LowerEXTRACT_VECTOR_ELT()
18636 int Mask[4] = { static_cast<int>(IdxVal), -1, -1, -1 }; in LowerEXTRACT_VECTOR_ELT()
18646 if (IdxVal == 0) in LowerEXTRACT_VECTOR_ELT()
18705 uint64_t IdxVal = N2C->getZExtValue(); in LowerINSERT_VECTOR_ELT() local
18717 BlendMask.push_back(i == IdxVal ? i + NumElts : i); in LowerINSERT_VECTOR_ELT()
18728 if (VT.is256BitVector() && IdxVal == 0) { in LowerINSERT_VECTOR_ELT()
18741 SDValue V = extract128BitVector(N0, IdxVal, DAG, dl); in LowerINSERT_VECTOR_ELT()
18747 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1); in LowerINSERT_VECTOR_ELT()
18753 return insert128BitVector(N0, V, IdxVal, DAG, dl); in LowerINSERT_VECTOR_ELT()
18758 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(N0.getNode())) { in LowerINSERT_VECTOR_ELT()
18791 N2 = DAG.getTargetConstant(IdxVal, dl, MVT::i8); in LowerINSERT_VECTOR_ELT()
18807 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) { in LowerINSERT_VECTOR_ELT()
18822 DAG.getTargetConstant(IdxVal << 4, dl, MVT::i8)); in LowerINSERT_VECTOR_ELT()
18885 uint64_t IdxVal = Op.getConstantOperandVal(1); in LowerEXTRACT_SUBVECTOR() local
18887 if (IdxVal == 0) // the operation is legal in LowerEXTRACT_SUBVECTOR()
18904 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in LowerEXTRACT_SUBVECTOR()
48979 uint64_t IdxVal = N->getConstantOperandVal(2); in combineInsertSubvector() local
48999 DAG.getIntPtrConstant(IdxVal + Idx2Val, dl)); in combineInsertSubvector()
49006 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && IdxVal == 0 && in combineInsertSubvector()
49028 (IdxVal != 0 || in combineInsertSubvector()
49040 Mask[i + IdxVal] = i + ExtIdxVal + VecNumElts; in combineInsertSubvector()
49066 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST) in combineInsertSubvector()
49071 if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() && in combineInsertSubvector()
49163 unsigned IdxVal = N->getConstantOperandVal(1); in combineExtractSubvector() local
49207 InVec.getNode()->ops().slice(IdxVal, VT.getVectorNumElements())); in combineExtractSubvector()
49213 InVec.getOpcode() == ISD::INSERT_SUBVECTOR && IdxVal == 0 && in combineExtractSubvector()
49247 if (IdxVal != 0 && (InVec.getOpcode() == X86ISD::VBROADCAST || in combineExtractSubvector()
49258 (IdxVal % VT.getVectorNumElements()) == 0) { in combineExtractSubvector()
49266 unsigned SubVecIdx = IdxVal / VT.getVectorNumElements(); in combineExtractSubvector()
49283 if (IdxVal == 0 && InVec.hasOneUse()) { in combineExtractSubvector()