66   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
492 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {  in Lower()
493   OutMI.setOpcode(MI->getOpcode());  in Lower()
497       OutMI.addOperand(MaybeMCOp.getValue());  in Lower()
500   switch (OutMI.getOpcode()) {  in Lower()
506     assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&  in Lower()
508     assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&  in Lower()
518     switch (OutMI.getOpcode()) {  in Lower()
525     OutMI.setOpcode(NewOpc);  in Lower()
527     unsigned DestReg = OutMI.getOperand(0).getReg();  in Lower()
528     OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg));  in Lower()
547     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&  in Lower()
548         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {  in Lower()
550       switch (OutMI.getOpcode()) {  in Lower()
566       OutMI.setOpcode(NewOpc);  in Lower()
572     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&  in Lower()
573         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {  in Lower()
575       switch (OutMI.getOpcode()) {  in Lower()
580       OutMI.setOpcode(NewOpc);  in Lower()
616     if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 0) {  in Lower()
618       switch (OutMI.getOpcode()) {  in Lower()
682       OutMI.setOpcode(NewOpc);  in Lower()
683       OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1));  in Lower()
688     if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 6) {  in Lower()
690       switch (OutMI.getOpcode()) {  in Lower()
754       OutMI.setOpcode(NewOpc);  in Lower()
755       OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1));  in Lower()
768     assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");  in Lower()
773     OutMI = MCInst();  in Lower()
774     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));  in Lower()
780     OutMI = MCInst();  in Lower()
781     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));  in Lower()
789     OutMI = MCInst();  in Lower()
790     OutMI.setOpcode(getRetOpcode(Subtarget));  in Lower()
791     OutMI.addOperand(MCOperand::createReg(ReturnReg));  in Lower()
802     assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");  in Lower()
803     OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));  in Lower()
808     assert(OutMI.getNumOperands() == 2 && "Unexpected number of operands!");  in Lower()
809     OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));  in Lower()
815     assert(OutMI.getNumOperands() == X86::AddrNumOperands &&  in Lower()
817     OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));  in Lower()
827       switch (OutMI.getOpcode()) {  in Lower()
834       OutMI.setOpcode(Opcode);  in Lower()
854     switch (OutMI.getOpcode()) {  in Lower()
865     SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);  in Lower()
879     switch (OutMI.getOpcode()) {  in Lower()
918     SimplifyShortImmForm(OutMI, NewOpc);  in Lower()
926     SimplifyMOVSX(OutMI);  in Lower()
937     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()) &&  in Lower()
938         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {  in Lower()
946         std::swap(OutMI.getOperand(1), OutMI.getOperand(2));  in Lower()
967         OutMI.getNumOperands() == 3) {  in Lower()
968       if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()) &&  in Lower()
969           X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg()))  in Lower()
970         std::swap(OutMI.getOperand(1), OutMI.getOperand(2));  in Lower()