Lines Matching refs:OPT
2 ; RUN: opt -codegenprepare -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s
17 ; OPT-LABEL: @foo(
18 ; OPT-NEXT: [[TMP:%.*]] = bitcast %struct.X* [[X:%.*]] to i32*
19 ; OPT-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 4
20 ; OPT-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_Y:%.*]], %struct.Y* [[Y:%.*]], i64 0, i3…
21 ; OPT-NEXT: [[BF_CLEAR:%.*]] = lshr i32 [[TMP1]], 3
22 ; OPT-NEXT: [[BF_CLEAR_LOBIT:%.*]] = and i32 [[BF_CLEAR]], 1
23 ; OPT-NEXT: [[FROMBOOL:%.*]] = trunc i32 [[BF_CLEAR_LOBIT]] to i8
24 ; OPT-NEXT: store i8 [[FROMBOOL]], i8* [[B]], align 1
25 ; OPT-NEXT: ret void
42 ; OPT-LABEL: @baz(
43 ; OPT-NEXT: [[TMP:%.*]] = trunc i64 [[CAV1_COERCE:%.*]] to i32
44 ; OPT-NEXT: [[TMP1:%.*]] = shl i32 [[TMP]], 28
45 ; OPT-NEXT: [[BF_VAL_SEXT:%.*]] = ashr exact i32 [[TMP1]], 28
46 ; OPT-NEXT: ret i32 [[BF_VAL_SEXT]]
59 ; OPT-LABEL: @bar(
60 ; OPT-NEXT: [[TMP:%.*]] = trunc i64 [[CAV1_COERCE:%.*]] to i32
61 ; OPT-NEXT: [[CAV1_SROA_0_1_INSERT:%.*]] = shl i32 [[TMP]], 22
62 ; OPT-NEXT: [[TMP1:%.*]] = ashr i32 [[CAV1_SROA_0_1_INSERT]], 26
63 ; OPT-NEXT: ret i32 [[TMP1]]
78 ; OPT-LABEL: @fct1(
79 ; OPT-NEXT: [[TMP:%.*]] = bitcast %struct.Z* [[X:%.*]] to i64*
80 ; OPT-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP]], align 4
81 ; OPT-NEXT: [[B1:%.*]] = bitcast %struct.A* [[Y:%.*]] to i64*
82 ; OPT-NEXT: [[BF_CLEAR:%.*]] = lshr i64 [[TMP1]], 3
83 ; OPT-NEXT: [[BF_CLEAR_LOBIT:%.*]] = and i64 [[BF_CLEAR]], 1
84 ; OPT-NEXT: store i64 [[BF_CLEAR_LOBIT]], i64* [[B1]], align 8
85 ; OPT-NEXT: ret void
101 ; OPT-LABEL: @fct2(
102 ; OPT-NEXT: [[TMP:%.*]] = shl i64 [[CAV1_COERCE:%.*]], 28
103 ; OPT-NEXT: [[BF_VAL_SEXT:%.*]] = ashr exact i64 [[TMP]], 28
104 ; OPT-NEXT: ret i64 [[BF_VAL_SEXT]]
116 ; OPT-LABEL: @fct3(
117 ; OPT-NEXT: [[CAV1_SROA_0_1_INSERT:%.*]] = shl i64 [[CAV1_COERCE:%.*]], 22
118 ; OPT-NEXT: [[TMP1:%.*]] = ashr i64 [[CAV1_SROA_0_1_INSERT]], 26
119 ; OPT-NEXT: ret i64 [[TMP1]]
133 ; OPT-LABEL: @fct4(
134 ; OPT-NEXT: entry:
135 ; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
136 ; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], -16777216
137 ; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 16
138 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 16777215
139 ; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
140 ; OPT-NEXT: store i64 [[OR]], i64* [[Y]], align 8
141 ; OPT-NEXT: ret void
160 ; OPT-LABEL: @fct5(
161 ; OPT-NEXT: entry:
162 ; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
163 ; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], -8
164 ; OPT-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 16
165 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
166 ; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
167 ; OPT-NEXT: store i32 [[OR]], i32* [[Y]], align 8
168 ; OPT-NEXT: ret void
189 ; OPT-LABEL: @fct6(
190 ; OPT-NEXT: entry:
191 ; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
192 ; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], -8
193 ; OPT-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 16
194 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
195 ; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
196 ; OPT-NEXT: [[SHR1:%.*]] = lshr i32 [[OR]], 2
197 ; OPT-NEXT: store i32 [[SHR1]], i32* [[Y]], align 8
198 ; OPT-NEXT: ret void
222 ; OPT-LABEL: @fct7(
223 ; OPT-NEXT: entry:
224 ; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
225 ; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], -8
226 ; OPT-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 16
227 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
228 ; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
229 ; OPT-NEXT: [[SHL:%.*]] = shl i32 [[OR]], 2
230 ; OPT-NEXT: store i32 [[SHL]], i32* [[Y]], align 8
231 ; OPT-NEXT: ret void
256 ; OPT-LABEL: @fct8(
257 ; OPT-NEXT: entry:
258 ; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
259 ; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], -8
260 ; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 16
261 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
262 ; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
263 ; OPT-NEXT: [[SHR1:%.*]] = lshr i64 [[OR]], 2
264 ; OPT-NEXT: store i64 [[SHR1]], i64* [[Y]], align 8
265 ; OPT-NEXT: ret void
290 ; OPT-LABEL: @fct9(
291 ; OPT-NEXT: entry:
292 ; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
293 ; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], -8
294 ; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 16
295 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
296 ; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
297 ; OPT-NEXT: [[SHL:%.*]] = shl i64 [[OR]], 2
298 ; OPT-NEXT: store i64 [[SHL]], i64* [[Y]], align 8
299 ; OPT-NEXT: ret void
323 ; OPT-LABEL: @fct10(
324 ; OPT-NEXT: entry:
325 ; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
326 ; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], -8
327 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[X:%.*]], 7
328 ; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
329 ; OPT-NEXT: [[SHL:%.*]] = shl i32 [[OR]], 2
330 ; OPT-NEXT: store i32 [[SHL]], i32* [[Y]], align 8
331 ; OPT-NEXT: ret void
354 ; OPT-LABEL: @fct11(
355 ; OPT-NEXT: entry:
356 ; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
357 ; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], -8
358 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[X:%.*]], 7
359 ; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
360 ; OPT-NEXT: [[SHL:%.*]] = shl i64 [[OR]], 2
361 ; OPT-NEXT: store i64 [[SHL]], i64* [[Y]], align 8
362 ; OPT-NEXT: ret void
380 ; OPT-LABEL: @fct12bis(
381 ; OPT-NEXT: [[AND_I_I:%.*]] = and i32 [[TMP2:%.*]], 2048
382 ; OPT-NEXT: [[TOBOOL_I_I:%.*]] = icmp ne i32 [[AND_I_I]], 0
383 ; OPT-NEXT: ret i1 [[TOBOOL_I_I]]
400 ; OPT-LABEL: @fct12(
401 ; OPT-NEXT: entry:
402 ; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
403 ; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], -8
404 ; OPT-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 16
405 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
406 ; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
407 ; OPT-NEXT: [[SHL:%.*]] = shl i32 [[OR]], 2
408 ; OPT-NEXT: [[SHR2:%.*]] = lshr i32 [[SHL]], 4
409 ; OPT-NEXT: store i32 [[SHR2]], i32* [[Y]], align 8
410 ; OPT-NEXT: ret void
433 ; OPT-LABEL: @fct12_mask(
434 ; OPT-NEXT: entry:
435 ; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
436 ; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], -8
437 ; OPT-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 16
438 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
439 ; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
440 ; OPT-NEXT: [[LSHR:%.*]] = lshr i32 [[OR]], 2
441 ; OPT-NEXT: [[MASK:%.*]] = and i32 [[LSHR]], 268435455
442 ; OPT-NEXT: store i32 [[MASK]], i32* [[Y]], align 8
443 ; OPT-NEXT: ret void
469 ; OPT-LABEL: @fct13(
470 ; OPT-NEXT: entry:
471 ; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
472 ; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], -8
473 ; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 16
474 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
475 ; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
476 ; OPT-NEXT: [[SHL:%.*]] = shl i64 [[OR]], 2
477 ; OPT-NEXT: [[SHR2:%.*]] = lshr i64 [[SHL]], 4
478 ; OPT-NEXT: store i64 [[SHR2]], i64* [[Y]], align 8
479 ; OPT-NEXT: ret void
502 ; OPT-LABEL: @fct13_mask(
503 ; OPT-NEXT: entry:
504 ; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
505 ; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], -8
506 ; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 16
507 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
508 ; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
509 ; OPT-NEXT: [[LSHR:%.*]] = lshr i64 [[OR]], 2
510 ; OPT-NEXT: [[MASK:%.*]] = and i64 [[LSHR]], 1152921504606846975
511 ; OPT-NEXT: store i64 [[MASK]], i64* [[Y]], align 8
512 ; OPT-NEXT: ret void
540 ; OPT-LABEL: @fct14(
541 ; OPT-NEXT: entry:
542 ; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
543 ; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], -256
544 ; OPT-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 16
545 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 255
546 ; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
547 ; OPT-NEXT: [[SHL:%.*]] = lshr i32 [[OR]], 4
548 ; OPT-NEXT: [[AND2:%.*]] = and i32 [[SHL]], -8
549 ; OPT-NEXT: [[SHR1:%.*]] = lshr i32 [[X1:%.*]], 5
550 ; OPT-NEXT: [[AND3:%.*]] = and i32 [[SHR1]], 7
551 ; OPT-NEXT: [[OR1:%.*]] = or i32 [[AND2]], [[AND3]]
552 ; OPT-NEXT: [[SHL1:%.*]] = shl i32 [[OR1]], 2
553 ; OPT-NEXT: store i32 [[SHL1]], i32* [[Y]], align 8
554 ; OPT-NEXT: ret void
587 ; OPT-LABEL: @fct15(
588 ; OPT-NEXT: entry:
589 ; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
590 ; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], -256
591 ; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 16
592 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 255
593 ; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
594 ; OPT-NEXT: [[SHL:%.*]] = lshr i64 [[OR]], 4
595 ; OPT-NEXT: [[AND2:%.*]] = and i64 [[SHL]], -8
596 ; OPT-NEXT: [[SHR1:%.*]] = lshr i64 [[X1:%.*]], 5
597 ; OPT-NEXT: [[AND3:%.*]] = and i64 [[SHR1]], 7
598 ; OPT-NEXT: [[OR1:%.*]] = or i64 [[AND2]], [[AND3]]
599 ; OPT-NEXT: [[SHL1:%.*]] = shl i64 [[OR1]], 2
600 ; OPT-NEXT: store i64 [[SHL1]], i64* [[Y]], align 8
601 ; OPT-NEXT: ret void
634 ; OPT-LABEL: @fct16(
635 ; OPT-NEXT: entry:
636 ; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
637 ; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], 1737056
638 ; OPT-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 16
639 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
640 ; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
641 ; OPT-NEXT: [[SHL:%.*]] = shl i32 [[OR]], 2
642 ; OPT-NEXT: [[SHR2:%.*]] = lshr i32 [[SHL]], 4
643 ; OPT-NEXT: store i32 [[SHR2]], i32* [[Y]], align 8
644 ; OPT-NEXT: ret void
671 ; OPT-LABEL: @fct16_mask(
672 ; OPT-NEXT: entry:
673 ; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
674 ; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], 1737056
675 ; OPT-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 16
676 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
677 ; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
678 ; OPT-NEXT: [[LSHR:%.*]] = lshr i32 [[OR]], 2
679 ; OPT-NEXT: [[MASK:%.*]] = and i32 [[LSHR]], 268435455
680 ; OPT-NEXT: store i32 [[MASK]], i32* [[Y]], align 8
681 ; OPT-NEXT: ret void
713 ; OPT-LABEL: @fct17(
714 ; OPT-NEXT: entry:
715 ; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
716 ; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], 1737056
717 ; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 16
718 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
719 ; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
720 ; OPT-NEXT: [[SHL:%.*]] = shl i64 [[OR]], 2
721 ; OPT-NEXT: [[SHR2:%.*]] = lshr i64 [[SHL]], 4
722 ; OPT-NEXT: store i64 [[SHR2]], i64* [[Y]], align 8
723 ; OPT-NEXT: ret void
750 ; OPT-LABEL: @fct17_mask(
751 ; OPT-NEXT: entry:
752 ; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
753 ; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], 1737056
754 ; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 16
755 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
756 ; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
757 ; OPT-NEXT: [[LSHR:%.*]] = lshr i64 [[OR]], 2
758 ; OPT-NEXT: [[MASK:%.*]] = and i64 [[LSHR]], 1152921504606846975
759 ; OPT-NEXT: store i64 [[MASK]], i64* [[Y]], align 8
760 ; OPT-NEXT: ret void
783 ; OPT-LABEL: @fct18(
784 ; OPT-NEXT: [[SHR81:%.*]] = lshr i32 [[XOR72:%.*]], 9
785 ; OPT-NEXT: [[CONV82:%.*]] = zext i32 [[SHR81]] to i64
786 ; OPT-NEXT: [[RESULT:%.*]] = and i64 [[CONV82]], 255
787 ; OPT-NEXT: ret i64 [[RESULT]]
830 ; OPT-LABEL: @fct19(
831 ; OPT-NEXT: entry:
832 ; OPT-NEXT: [[X_SROA_1_0_EXTRACT_SHIFT:%.*]] = lshr i64 [[ARG1:%.*]], 16
833 ; OPT-NEXT: [[X_SROA_1_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[X_SROA_1_0_EXTRACT_SHIFT]] to i16
834 ; OPT-NEXT: [[X_SROA_5_0_EXTRACT_SHIFT:%.*]] = lshr i64 [[ARG1]], 48
835 ; OPT-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[X_SROA_5_0_EXTRACT_SHIFT]], 0
836 ; OPT-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
837 ; OPT: if.then:
838 ; OPT-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [65536 x i8], [65536 x i8]* @first_ones, …
839 ; OPT-NEXT: [[TMP0:%.*]] = load i8, i8* [[ARRAYIDX3]], align 1
840 ; OPT-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
841 ; OPT-NEXT: br label [[RETURN:%.*]]
842 ; OPT: if.end:
843 ; OPT-NEXT: [[TMP1:%.*]] = lshr i64 [[ARG1]], 32
844 ; OPT-NEXT: [[X_SROA_3_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[TMP1]] to i16
845 ; OPT-NEXT: [[TOBOOL6:%.*]] = icmp eq i16 [[X_SROA_3_0_EXTRACT_TRUNC]], 0
846 ; OPT-NEXT: br i1 [[TOBOOL6]], label [[IF_END13:%.*]], label [[IF_THEN7:%.*]]
847 ; OPT: if.then7:
848 ; OPT-NEXT: [[TMP2:%.*]] = lshr i64 [[ARG1]], 32
849 ; OPT-NEXT: [[IDXPROM10:%.*]] = and i64 [[TMP2]], 65535
850 ; OPT-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [65536 x i8], [65536 x i8]* @first_ones,…
851 ; OPT-NEXT: [[TMP3:%.*]] = load i8, i8* [[ARRAYIDX11]], align 1
852 ; OPT-NEXT: [[CONV12:%.*]] = zext i8 [[TMP3]] to i32
853 ; OPT-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV12]], 16
854 ; OPT-NEXT: br label [[RETURN]]
855 ; OPT: if.end13:
856 ; OPT-NEXT: [[TMP4:%.*]] = lshr i64 [[ARG1]], 16
857 ; OPT-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i16
858 ; OPT-NEXT: [[TOBOOL16:%.*]] = icmp eq i16 [[TMP5]], 0
859 ; OPT-NEXT: br i1 [[TOBOOL16]], label [[RETURN]], label [[IF_THEN17:%.*]]
860 ; OPT: if.then17:
861 ; OPT-NEXT: [[TMP6:%.*]] = lshr i64 [[ARG1]], 16
862 ; OPT-NEXT: [[IDXPROM20:%.*]] = and i64 [[TMP6]], 65535
863 ; OPT-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [65536 x i8], [65536 x i8]* @first_ones,…
864 ; OPT-NEXT: [[TMP7:%.*]] = load i8, i8* [[ARRAYIDX21]], align 1
865 ; OPT-NEXT: [[CONV22:%.*]] = zext i8 [[TMP7]] to i32
866 ; OPT-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 32
867 ; OPT-NEXT: br label [[RETURN]]
868 ; OPT: return:
869 ; OPT-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CONV]], [[IF_THEN]] ], [ [[ADD]], [[IF_THEN7]] ], [ […
870 ; OPT-NEXT: ret i32 [[RETVAL_0]]
939 ; OPT-LABEL: @fct20(
940 ; OPT-NEXT: entry:
941 ; OPT-NEXT: [[SHR:%.*]] = lshr i128 [[A:%.*]], 18
942 ; OPT-NEXT: [[CONV:%.*]] = trunc i128 [[SHR]] to i80
943 ; OPT-NEXT: [[TOBOOL:%.*]] = icmp eq i128 [[B:%.*]], 0
944 ; OPT-NEXT: br i1 [[TOBOOL]], label [[THEN:%.*]], label [[END:%.*]]
945 ; OPT: then:
946 ; OPT-NEXT: [[AND:%.*]] = and i128 [[SHR]], 483673642326615442599424
947 ; OPT-NEXT: [[CONV2:%.*]] = trunc i128 [[AND]] to i80
948 ; OPT-NEXT: br label [[END]]
949 ; OPT: end:
950 ; OPT-NEXT: [[CONV3:%.*]] = phi i80 [ [[CONV]], [[ENTRY:%.*]] ], [ [[CONV2]], [[THEN]] ]
951 ; OPT-NEXT: ret i80 [[CONV3]]
977 ; OPT-LABEL: @fct21(
978 ; OPT-NEXT: entry:
979 ; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 4
980 ; OPT-NEXT: [[AND:%.*]] = and i64 [[SHR]], 15
981 ; OPT-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [8 x [64 x i64]], [8 x [64 x i64]]* @arr, …
982 ; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[ARRAYIDX]], align 8
983 ; OPT-NEXT: ret i64 [[TMP0]]
1000 ; OPT-LABEL: @test_ignored_rightbits(
1001 ; OPT-NEXT: [[POSITIONED_FIELD:%.*]] = shl i32 [[IN:%.*]], 3
1002 ; OPT-NEXT: [[POSITIONED_MASKED_FIELD:%.*]] = and i32 [[POSITIONED_FIELD]], 120
1003 ; OPT-NEXT: [[MASKED_DST:%.*]] = and i32 [[DST:%.*]], 7
1004 ; OPT-NEXT: [[INSERTION:%.*]] = or i32 [[MASKED_DST]], [[POSITIONED_MASKED_FIELD]]
1005 ; OPT-NEXT: [[SHL16:%.*]] = shl i32 [[INSERTION]], 8
1006 ; OPT-NEXT: [[OR18:%.*]] = or i32 [[SHL16]], [[INSERTION]]
1007 ; OPT-NEXT: [[CONV19:%.*]] = trunc i32 [[OR18]] to i16
1008 ; OPT-NEXT: ret i16 [[CONV19]]
1037 ; OPT-LABEL: @sameOperandBFI(
1038 ; OPT-NEXT: entry:
1039 ; OPT-NEXT: [[SHR47:%.*]] = lshr i64 [[SRC:%.*]], 47
1040 ; OPT-NEXT: [[SRC2_TRUNC:%.*]] = trunc i64 [[SRC2:%.*]] to i32
1041 ; OPT-NEXT: br i1 undef, label [[END:%.*]], label [[IF_ELSE:%.*]]
1042 ; OPT: if.else:
1043 ; OPT-NEXT: [[AND3:%.*]] = and i32 [[SRC2_TRUNC]], 3
1044 ; OPT-NEXT: [[SHL2:%.*]] = shl nuw nsw i64 [[SHR47]], 2
1045 ; OPT-NEXT: [[SHL2_TRUNC:%.*]] = trunc i64 [[SHL2]] to i32
1046 ; OPT-NEXT: [[AND12:%.*]] = and i32 [[SHL2_TRUNC]], 12
1047 ; OPT-NEXT: [[BFISOURCE:%.*]] = or i32 [[AND3]], [[AND12]]
1048 ; OPT-NEXT: [[BFIRHS:%.*]] = shl nuw nsw i32 [[BFISOURCE]], 4
1049 ; OPT-NEXT: [[BFI:%.*]] = or i32 [[BFIRHS]], [[BFISOURCE]]
1050 ; OPT-NEXT: [[BFITRUNC:%.*]] = trunc i32 [[BFI]] to i16
1051 ; OPT-NEXT: store i16 [[BFITRUNC]], i16* [[PTR:%.*]], align 4
1052 ; OPT-NEXT: br label [[END]]
1053 ; OPT: end:
1054 ; OPT-NEXT: ret void