Lines Matching +full:- +full:4
1 …RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --chec…
2 …RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --chec…
4 define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
6 ; CHECK-CVT-LABEL: add_h:
7 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
8 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
9 ; CHECK-CVT-NEXT: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
10 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[RES]]
12 ; CHECK-FP16-LABEL: add_h:
13 ; CHECK-FP16: fadd v0.4h, v0.4h, v1.4h
14 ; CHECK-FP16-NEXT: ret
15 %0 = fadd <4 x half> %a, %b
16 ret <4 x half> %0
20 define <4 x half> @build_h4(<4 x half> %a) {
22 ; CHECK-COMMON-LABEL: build_h4:
23 ; CHECK-COMMON: mov [[GPR:w[0-9]+]], #15565
24 ; CHECK-COMMON-NEXT: dup v0.4h, [[GPR]]
25 ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>
29 define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
31 ; CHECK-CVT-LABEL: sub_h:
32 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
33 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
34 ; CHECK-CVT-NEXT: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
35 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[RES]]
37 ; CHECK-FP16-LABEL: sub_h:
38 ; CHECK-FP16: fsub v0.4h, v0.4h, v1.4h
39 ; CHECK-FP16-NEXT: ret
40 %0 = fsub <4 x half> %a, %b
41 ret <4 x half> %0
45 define <4 x half> @mul_h(<4 x half> %a, <4 x half> %b) {
47 ; CHECK-CVT-LABEL: mul_h:
48 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
49 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
50 ; CHECK-CVT-NEXT: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
51 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[RES]]
53 ; CHECK-FP16-LABEL: mul_h:
54 ; CHECK-FP16: fmul v0.4h, v0.4h, v1.4h
55 ; CHECK-FP16-NEXT: ret
56 %0 = fmul <4 x half> %a, %b
57 ret <4 x half> %0
61 define <4 x half> @div_h(<4 x half> %a, <4 x half> %b) {
63 ; CHECK-CVT-LABEL: div_h:
64 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
65 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
66 ; CHECK-CVT-NEXT: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
67 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[RES]]
69 ; CHECK-FP16-LABEL: div_h:
70 ; CHECK-FP16: fdiv v0.4h, v0.4h, v1.4h
71 ; CHECK-FP16-NEXT: ret
72 %0 = fdiv <4 x half> %a, %b
73 ret <4 x half> %0
77 define <4 x half> @load_h(<4 x half>* %a) {
79 ; CHECK-COMMON-LABEL: load_h:
80 ; CHECK-COMMON: ldr d0, [x0]
81 ; CHECK-COMMON-NEXT: ret
82 %0 = load <4 x half>, <4 x half>* %a, align 4
83 ret <4 x half> %0
87 define void @store_h(<4 x half>* %a, <4 x half> %b) {
89 ; CHECK-COMMON-LABEL: store_h:
90 ; CHECK-COMMON: str d0, [x0]
91 ; CHECK-COMMON-NEXT: ret
92 store <4 x half> %b, <4 x half>* %a, align 4
96 define <4 x half> @s_to_h(<4 x float> %a) {
97 ; CHECK-COMMON-LABEL: s_to_h:
98 ; CHECK-COMMON: fcvtn v0.4h, v0.4s
99 ; CHECK-COMMON-NEXT: ret
100 %1 = fptrunc <4 x float> %a to <4 x half>
101 ret <4 x half> %1
104 define <4 x half> @d_to_h(<4 x double> %a) {
105 ; CHECK-LABEL: d_to_h:
106 ; CHECK-DAG: fcvt h
107 ; CHECK-DAG: fcvt h
108 ; CHECK-DAG: fcvt h
109 ; CHECK-DAG: fcvt h
110 ; CHECK-DAG: mov v{{[0-9]+}}.h
111 ; CHECK-DAG: mov v{{[0-9]+}}.h
112 ; CHECK-DAG: mov v{{[0-9]+}}.h
113 ; CHECK-DAG: mov v{{[0-9]+}}.h
114 %1 = fptrunc <4 x double> %a to <4 x half>
115 ret <4 x half> %1
118 define <4 x float> @h_to_s(<4 x half> %a) {
119 ; CHECK-COMMON-LABEL: h_to_s:
120 ; CHECK-COMMON: fcvtl v0.4s, v0.4h
121 ; CHECK-COMMON-NEXT: ret
122 %1 = fpext <4 x half> %a to <4 x float>
123 ret <4 x float> %1
126 define <4 x double> @h_to_d(<4 x half> %a) {
127 ; CHECK-LABEL: h_to_d:
128 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
129 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
130 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
131 ; CHECK-DAG: fcvt
132 ; CHECK-DAG: fcvt
133 ; CHECK-DAG: fcvt
134 ; CHECK-DAG: fcvt
135 %1 = fpext <4 x half> %a to <4 x double>
136 ret <4 x double> %1
139 define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) {
140 ; CHECK-COMMON-LABEL: bitcast_i_to_h:
141 ; CHECK-COMMON: mov v0.16b, v1.16b
142 ; CHECK-COMMON-NEXT: ret
143 %2 = bitcast <4 x i16> %a to <4 x half>
144 ret <4 x half> %2
147 define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {
148 ; CHECK-COMMON-LABEL: bitcast_h_to_i:
149 ; CHECK-COMMON: mov v0.16b, v1.16b
150 ; CHECK-COMMON-NEXT: ret
151 %2 = bitcast <4 x half> %a to <4 x i16>
152 ret <4 x i16> %2
155 define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {
156 ; CHECK-COMMON-LABEL: sitofp_i8:
157 ; CHECK-COMMON-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
158 ; CHECK-COMMON-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
159 ; CHECK-FP16-NEXT: scvtf v0.4h, [[OP2]]
160 ; CHECK-CVT-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
161 ; CHECK-CVT-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
162 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[OP4]]
163 ; CHECK-COMMON-NEXT: ret
164 %1 = sitofp <4 x i8> %a to <4 x half>
165 ret <4 x half> %1
168 define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {
169 ; CHECK-COMMON-LABEL: sitofp_i16:
170 ; CHECK-FP16-NEXT: scvtf v0.4h, v0.4h
171 ; CHECK-CVT-NEXT: sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
172 ; CHECK-CVT-NEXT: scvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
173 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[OP2]]
174 ; CHECK-COMMON-NEXT: ret
175 %1 = sitofp <4 x i16> %a to <4 x half>
176 ret <4 x half> %1
180 define <4 x half> @sitofp_i32(<4 x i32> %a) #0 {
181 ; CHECK-COMMON-LABEL: sitofp_i32:
182 ; CHECK-COMMON-NEXT: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
183 ; CHECK-COMMON-NEXT: fcvtn v0.4h, [[OP1]]
184 ; CHECK-COMMON-NEXT: ret
185 %1 = sitofp <4 x i32> %a to <4 x half>
186 ret <4 x half> %1
190 define <4 x half> @sitofp_i64(<4 x i64> %a) #0 {
191 ; CHECK-COMMON-LABEL: sitofp_i64:
192 ; CHECK-COMMON-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
193 ; CHECK-COMMON-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
194 ; CHECK-COMMON-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
195 ; CHECK-COMMON-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
196 ; CHECK-COMMON-NEXT: fcvtn v0.4h, [[OP3]].4s
197 ; CHECK-COMMON-NEXT: ret
198 %1 = sitofp <4 x i64> %a to <4 x half>
199 ret <4 x half> %1
202 define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {
203 ; CHECK-COMMON-LABEL: uitofp_i8:
204 ; CHECK-COMMON-NEXT: bic v0.4h, #255, lsl #8
205 ; CHECK-FP16-NEXT: ucvtf v0.4h, v0.4h
206 ; CHECK-CVT-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
207 ; CHECK-CVT-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
208 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[OP2]]
209 ; CHECK-COMMON-NEXT: ret
210 %1 = uitofp <4 x i8> %a to <4 x half>
211 ret <4 x half> %1
215 define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {
216 ; CHECK-COMMON-LABEL: uitofp_i16:
217 ; CHECK-FP16-NEXT: ucvtf v0.4h, v0.4h
218 ; CHECK-CVT-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
219 ; CHECK-CVT-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
220 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[OP2]]
221 ; CHECK-COMMON-NEXT: ret
222 %1 = uitofp <4 x i16> %a to <4 x half>
223 ret <4 x half> %1
227 define <4 x half> @uitofp_i32(<4 x i32> %a) #0 {
228 ; CHECK-COMMON-LABEL: uitofp_i32:
229 ; CHECK-COMMON-NEXT: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
230 ; CHECK-COMMON-NEXT: fcvtn v0.4h, [[OP1]]
231 ; CHECK-COMMON-NEXT: ret
232 %1 = uitofp <4 x i32> %a to <4 x half>
233 ret <4 x half> %1
237 define <4 x half> @uitofp_i64(<4 x i64> %a) #0 {
238 ; CHECK-COMMON-LABEL: uitofp_i64:
239 ; CHECK-COMMON-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
240 ; CHECK-COMMON-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
241 ; CHECK-COMMON-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
242 ; CHECK-COMMON-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
243 ; CHECK-COMMON-NEXT: fcvtn v0.4h, [[OP3]].4s
244 ; CHECK-COMMON-NEXT: ret
245 %1 = uitofp <4 x i64> %a to <4 x half>
246 ret <4 x half> %1
249 define void @test_insert_at_zero(half %a, <4 x half>* %b) #0 {
250 ; CHECK-COMMON-LABEL: test_insert_at_zero:
251 ; CHECK-COMMON-NEXT: str d0, [x0]
252 ; CHECK-COMMON-NEXT: ret
253 %1 = insertelement <4 x half> undef, half %a, i64 0
254 store <4 x half> %1, <4 x half>* %b, align 4
258 define <4 x i8> @fptosi_i8(<4 x half> %a) #0 {
259 ; CHECK-COMMON-LABEL: fptosi_i8:
260 ; CHECK-FP16: fcvtzs v0.4h, v0.4h
261 ; CHECK-CVT-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
262 ; CHECK-CVT-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
263 ; CHECK-CVT-NEXT: xtn v0.4h, [[REG2]]
264 ; CHECK-COMMON-NEXT: ret
265 %1 = fptosi<4 x half> %a to <4 x i8>
266 ret <4 x i8> %1
269 define <4 x i16> @fptosi_i16(<4 x half> %a) #0 {
270 ; CHECK-COMMON-LABEL: fptosi_i16:
271 ; CHECK-FP16: fcvtzs v0.4h, v0.4h
272 ; CHECK-CVT-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
273 ; CHECK-CVT-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
274 ; CHECK-CVT-NEXT: xtn v0.4h, [[REG2]]
275 ; CHECK-COMMON-NEXT: ret
276 %1 = fptosi<4 x half> %a to <4 x i16>
277 ret <4 x i16> %1
280 define <4 x i8> @fptoui_i8(<4 x half> %a) #0 {
281 ; CHECK-COMMON-LABEL: fptoui_i8:
282 ; CHECK-FP16: fcvtzs v0.4h, v0.4h
283 ; CHECK-CVT-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
285 ; CHECK-CVT-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
286 ; CHECK-CVT-NEXT: xtn v0.4h, [[REG2]]
287 ; CHECK-COMMON-NEXT: ret
288 %1 = fptoui<4 x half> %a to <4 x i8>
289 ret <4 x i8> %1
292 define <4 x i16> @fptoui_i16(<4 x half> %a) #0 {
293 ; CHECK-COMMON-LABEL: fptoui_i16:
294 ; CHECK-FP16: fcvtzu v0.4h, v0.4h
295 ; CHECK-CVT-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
296 ; CHECK-CVT-NEXT: fcvtzu [[REG2:v[0-9]+\.4s]], [[REG1]]
297 ; CHECK-CVT-NEXT: xtn v0.4h, [[REG2]]
298 ; CHECK-COMMON-NEXT: ret
299 %1 = fptoui<4 x half> %a to <4 x i16>
300 ret <4 x i16> %1
303 define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 {
304 ; CHECK-CVT-LABEL: test_fcmp_une:
305 ; CHECK-CVT: fcvtl
306 ; CHECK-CVT: fcvtl
307 ; CHECK-CVT: fcmeq
308 ; CHECK-CVT: mvn
309 ; CHECK-CVT: xtn
310 ; CHECK-CVT: ret
312 ; CHECK-FP16-LABEL: test_fcmp_une:
313 ; CHECK-FP16-NOT: fcvt
314 ; CHECK-FP16: fcmeq v{{[0-9]}}.4h, v{{[0-9]}}.4h
315 %1 = fcmp une <4 x half> %a, %b
316 ret <4 x i1> %1
319 define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {
320 ; CHECK-CVT-LABEL: test_fcmp_ueq:
321 ; CHECK-CVT: fcvtl
322 ; CHECK-CVT: fcvtl
323 ; CHECK-CVT: fcmgt
324 ; CHECK-CVT: fcmgt
325 ; CHECK-CVT: orr
326 ; CHECK-CVT: xtn
327 ; CHECK-CVT: mvn
328 ; CHECK-CVT: ret
330 ; CHECK-FP16-LABEL: test_fcmp_ueq:
331 ; CHECK-FP16-NOT: fcvt
332 ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
333 ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
334 %1 = fcmp ueq <4 x half> %a, %b
335 ret <4 x i1> %1
338 define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 {
339 ; CHECK-CVT-LABEL: test_fcmp_ugt:
340 ; CHECK-CVT: fcvtl
341 ; CHECK-CVT: fcvtl
342 ; CHECK-CVT: fcmge
343 ; CHECK-CVT: xtn
344 ; CHECK-CVT: mvn
345 ; CHECK-CVT: ret
347 ; CHECK-FP16-LABEL: test_fcmp_ugt:
348 ; CHECK-FP16-NOT: fcvt
349 ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
350 %1 = fcmp ugt <4 x half> %a, %b
351 ret <4 x i1> %1
354 define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 {
355 ; CHECK-CVT-LABEL: test_fcmp_uge:
356 ; CHECK-CVT: fcvtl
357 ; CHECK-CVT: fcvtl
358 ; CHECK-CVT: fcmgt
359 ; CHECK-CVT: xtn
360 ; CHECK-CVT: mvn
361 ; CHECK-CVT: ret
363 ; CHECK-FP16-LABEL: test_fcmp_uge:
364 ; CHECK-FP16-NOT: fcvt
365 ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
366 %1 = fcmp uge <4 x half> %a, %b
367 ret <4 x i1> %1
370 define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 {
371 ; CHECK-CVT-LABEL: test_fcmp_ult:
372 ; CHECK-CVT: fcvtl
373 ; CHECK-CVT: fcvtl
374 ; CHECK-CVT: fcmge
375 ; CHECK-CVT: xtn
376 ; CHECK-CVT: mvn
377 ; CHECK-CVT: ret
379 ; CHECK-FP16-LABEL: test_fcmp_ult:
380 ; CHECK-FP16-NOT: fcvt
381 ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
382 %1 = fcmp ult <4 x half> %a, %b
383 ret <4 x i1> %1
386 define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 {
387 ; CHECK-CVT-LABEL: test_fcmp_ule:
388 ; CHECK-CVT: fcvtl
389 ; CHECK-CVT: fcvtl
390 ; CHECK-CVT: fcmgt
391 ; CHECK-CVT: xtn
392 ; CHECK-CVT: mvn
393 ; CHECK-CVT: ret
395 ; CHECK-FP16-LABEL: test_fcmp_ule:
396 ; CHECK-FP16-NOT: fcvt
397 ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
398 %1 = fcmp ule <4 x half> %a, %b
399 ret <4 x i1> %1
402 define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {
403 ; CHECK-CVT-LABEL: test_fcmp_uno:
404 ; CHECK-CVT: fcvtl
405 ; CHECK-CVT: fcvtl
406 ; CHECK-CVT: fcmge
407 ; CHECK-CVT: fcmgt
408 ; CHECK-CVT: orr
409 ; CHECK-CVT: xtn
410 ; CHECK-CVT: mvn
411 ; CHECK-CVT: ret
413 ; CHECK-FP16-LABEL: test_fcmp_uno:
414 ; CHECK-FP16-NOT: fcvt
415 ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
416 ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
417 %1 = fcmp uno <4 x half> %a, %b
418 ret <4 x i1> %1
421 define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 {
422 ; CHECK-CVT-LABEL: test_fcmp_one:
423 ; CHECK-CVT: fcvtl
424 ; CHECK-CVT: fcvtl
425 ; CHECK-CVT: fcmgt
426 ; CHECK-CVT: fcmgt
427 ; CHECK-CVT: orr
428 ; CHECK-CVT: xtn
429 ; CHECK-CVT: ret
431 ; CHECK-FP16-LABEL: test_fcmp_one:
432 ; CHECK-FP16-NOT: fcvt
433 ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
434 ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
435 %1 = fcmp one <4 x half> %a, %b
436 ret <4 x i1> %1
439 define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 {
440 ; CHECK-CVT-LABEL: test_fcmp_oeq:
441 ; CHECK-CVT: fcvtl
442 ; CHECK-CVT: fcvtl
443 ; CHECK-CVT: fcmeq
444 ; CHECK-CVT: xtn
445 ; CHECK-CVT: ret
447 ; CHECK-FP16-LABEL: test_fcmp_oeq:
448 ; CHECK-FP16-NOT: fcvt
449 ; CHECK-FP16: fcmeq v{{[0-9]}}.4h, v{{[0-9]}}.4h
450 %1 = fcmp oeq <4 x half> %a, %b
451 ret <4 x i1> %1
454 define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 {
455 ; CHECK-CVT-LABEL: test_fcmp_ogt:
456 ; CHECK-CVT: fcvtl
457 ; CHECK-CVT: fcvtl
458 ; CHECK-CVT: fcmgt
459 ; CHECK-CVT: xtn
460 ; CHECK-CVT: ret
462 ; CHECK-FP16-LABEL: test_fcmp_ogt:
463 ; CHECK-FP16-NOT: fcvt
464 ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
465 %1 = fcmp ogt <4 x half> %a, %b
466 ret <4 x i1> %1
469 define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 {
470 ; CHECK-CVT-LABEL: test_fcmp_oge:
471 ; CHECK-CVT: fcvtl
472 ; CHECK-CVT: fcvtl
473 ; CHECK-CVT: fcmge
474 ; CHECK-CVT: xtn
475 ; CHECK-CVT: ret
477 ; CHECK-FP16-LABEL: test_fcmp_oge:
478 ; CHECK-FP16-NOT: fcvt
479 ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
480 %1 = fcmp oge <4 x half> %a, %b
481 ret <4 x i1> %1
484 define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 {
485 ; CHECK-CVT-LABEL: test_fcmp_olt:
486 ; CHECK-CVT: fcvtl
487 ; CHECK-CVT: fcvtl
488 ; CHECK-CVT: fcmgt
489 ; CHECK-CVT: xtn
490 ; CHECK-CVT: ret
492 ; CHECK-FP16-LABEL: test_fcmp_olt:
493 ; CHECK-FP16-NOT: fcvt
494 ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
495 %1 = fcmp olt <4 x half> %a, %b
496 ret <4 x i1> %1
499 define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 {
500 ; CHECK-CVT-LABEL: test_fcmp_ole:
501 ; CHECK-CVT: fcvtl
502 ; CHECK-CVT: fcvtl
503 ; CHECK-CVT: fcmge
504 ; CHECK-CVT: xtn
505 ; CHECK-CVT: ret
507 ; CHECK-FP16-LABEL: test_fcmp_ole:
508 ; CHECK-FP16-NOT: fcvt
509 ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
510 %1 = fcmp ole <4 x half> %a, %b
511 ret <4 x i1> %1
514 define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 {
515 ; CHECK-CVT-LABEL: test_fcmp_ord:
516 ; CHECK-CVT: fcvtl
517 ; CHECK-CVT: fcvtl
518 ; CHECK-CVT: fcmge
519 ; CHECK-CVT: fcmgt
520 ; CHECK-CVT: orr
521 ; CHECK-CVT: xtn
522 ; CHECK-CVT: ret
524 ; CHECK-FP16-LABEL: test_fcmp_ord:
525 ; CHECK-FP16-NOT: fcvt
526 ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
527 ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
528 %1 = fcmp ord <4 x half> %a, %b
529 ret <4 x i1> %1