Lines Matching +full:- +full:4

2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
5 define <4 x i32> @test_urem_odd_even(<4 x i32> %X) nounwind {
6 ; CHECK-LABEL: test_urem_odd_even:
8 ; CHECK-NEXT:    adrp x8, .LCPI0_0
9 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
10 ; CHECK-NEXT:    adrp x8, .LCPI0_1
11 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI0_1]
12 ; CHECK-NEXT:    adrp x8, .LCPI0_2
13 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI0_2]
14 ; CHECK-NEXT:    neg v1.4s, v1.4s
15 ; CHECK-NEXT:    adrp x8, .LCPI0_3
16 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
17 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
18 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
19 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI0_3]
20 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
21 ; CHECK-NEXT:    neg v3.4s, v3.4s
22 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
23 ; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
24 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
25 ; CHECK-NEXT:    movi v1.4s, #1
26 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
27 ; CHECK-NEXT:    ret
28   %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100>
29   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
30   %ret = zext <4 x i1> %cmp to <4 x i32>
31   ret <4 x i32> %ret
36 ; One all-ones divisor in odd divisor
37 define <4 x i32> @test_urem_odd_allones_eq(<4 x i32> %X) nounwind {
38 ; CHECK-LABEL: test_urem_odd_allones_eq:
40 ; CHECK-NEXT:    adrp x8, .LCPI1_0
41 ; CHECK-NEXT:    adrp x9, .LCPI1_1
42 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
43 ; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI1_1]
44 ; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
45 ; CHECK-NEXT:    cmhs v0.4s, v2.4s, v0.4s
46 ; CHECK-NEXT:    movi v1.4s, #1
47 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
48 ; CHECK-NEXT:    ret
49   %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
50   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
51   %ret = zext <4 x i1> %cmp to <4 x i32>
52   ret <4 x i32> %ret
54 define <4 x i32> @test_urem_odd_allones_ne(<4 x i32> %X) nounwind {
55 ; CHECK-LABEL: test_urem_odd_allones_ne:
57 ; CHECK-NEXT:    adrp x8, .LCPI2_0
58 ; CHECK-NEXT:    adrp x9, .LCPI2_1
59 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
60 ; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI2_1]
61 ; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
62 ; CHECK-NEXT:    cmhi v0.4s, v0.4s, v2.4s
63 ; CHECK-NEXT:    movi v1.4s, #1
64 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
65 ; CHECK-NEXT:    ret
66   %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
67   %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
68   %ret = zext <4 x i1> %cmp to <4 x i32>
69   ret <4 x i32> %ret
72 ; One all-ones divisor in even divisor
73 define <4 x i32> @test_urem_even_allones_eq(<4 x i32> %X) nounwind {
74 ; CHECK-LABEL: test_urem_even_allones_eq:
76 ; CHECK-NEXT:    adrp x8, .LCPI3_0
77 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
78 ; CHECK-NEXT:    adrp x8, .LCPI3_1
79 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI3_1]
80 ; CHECK-NEXT:    adrp x8, .LCPI3_2
81 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI3_2]
82 ; CHECK-NEXT:    neg v1.4s, v1.4s
83 ; CHECK-NEXT:    adrp x8, .LCPI3_3
84 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
85 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
86 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
87 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI3_3]
88 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
89 ; CHECK-NEXT:    neg v3.4s, v3.4s
90 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
91 ; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
92 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
93 ; CHECK-NEXT:    movi v1.4s, #1
94 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
95 ; CHECK-NEXT:    ret
96   %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
97   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
98   %ret = zext <4 x i1> %cmp to <4 x i32>
99   ret <4 x i32> %ret
101 define <4 x i32> @test_urem_even_allones_ne(<4 x i32> %X) nounwind {
102 ; CHECK-LABEL: test_urem_even_allones_ne:
104 ; CHECK-NEXT:    adrp x8, .LCPI4_0
105 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
106 ; CHECK-NEXT:    adrp x8, .LCPI4_1
107 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI4_1]
108 ; CHECK-NEXT:    adrp x8, .LCPI4_2
109 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI4_2]
110 ; CHECK-NEXT:    neg v1.4s, v1.4s
111 ; CHECK-NEXT:    adrp x8, .LCPI4_3
112 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
113 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
114 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
115 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI4_3]
116 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
117 ; CHECK-NEXT:    neg v3.4s, v3.4s
118 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
119 ; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
120 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
121 ; CHECK-NEXT:    movi v1.4s, #1
122 ; CHECK-NEXT:    bic v0.16b, v1.16b, v0.16b
123 ; CHECK-NEXT:    ret
124   %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
125   %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
126   %ret = zext <4 x i1> %cmp to <4 x i32>
127   ret <4 x i32> %ret
130 ; One all-ones divisor in odd+even divisor
131 define <4 x i32> @test_urem_odd_even_allones_eq(<4 x i32> %X) nounwind {
132 ; CHECK-LABEL: test_urem_odd_even_allones_eq:
134 ; CHECK-NEXT:    adrp x8, .LCPI5_0
135 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_0]
136 ; CHECK-NEXT:    adrp x8, .LCPI5_1
137 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI5_1]
138 ; CHECK-NEXT:    adrp x8, .LCPI5_2
139 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI5_2]
140 ; CHECK-NEXT:    neg v1.4s, v1.4s
141 ; CHECK-NEXT:    adrp x8, .LCPI5_3
142 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
143 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
144 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
145 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI5_3]
146 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
147 ; CHECK-NEXT:    neg v3.4s, v3.4s
148 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
149 ; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
150 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
151 ; CHECK-NEXT:    movi v1.4s, #1
152 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
153 ; CHECK-NEXT:    ret
154   %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
155   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
156   %ret = zext <4 x i1> %cmp to <4 x i32>
157   ret <4 x i32> %ret
159 define <4 x i32> @test_urem_odd_even_allones_ne(<4 x i32> %X) nounwind {
160 ; CHECK-LABEL: test_urem_odd_even_allones_ne:
162 ; CHECK-NEXT:    adrp x8, .LCPI6_0
163 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI6_0]
164 ; CHECK-NEXT:    adrp x8, .LCPI6_1
165 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI6_1]
166 ; CHECK-NEXT:    adrp x8, .LCPI6_2
167 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI6_2]
168 ; CHECK-NEXT:    neg v1.4s, v1.4s
169 ; CHECK-NEXT:    adrp x8, .LCPI6_3
170 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
171 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
172 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
173 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI6_3]
174 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
175 ; CHECK-NEXT:    neg v3.4s, v3.4s
176 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
177 ; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
178 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
179 ; CHECK-NEXT:    movi v1.4s, #1
180 ; CHECK-NEXT:    bic v0.16b, v1.16b, v0.16b
181 ; CHECK-NEXT:    ret
182   %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
183   %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
184   %ret = zext <4 x i1> %cmp to <4 x i32>
185   ret <4 x i32> %ret
188 ;------------------------------------------------------------------------------;
190 ; One power-of-two divisor in odd divisor
191 define <4 x i32> @test_urem_odd_poweroftwo(<4 x i32> %X) nounwind {
192 ; CHECK-LABEL: test_urem_odd_poweroftwo:
194 ; CHECK-NEXT:    adrp x8, .LCPI7_0
195 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI7_0]
196 ; CHECK-NEXT:    adrp x8, .LCPI7_1
197 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI7_1]
198 ; CHECK-NEXT:    adrp x8, .LCPI7_2
199 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI7_2]
200 ; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
201 ; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
202 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
203 ; CHECK-NEXT:    neg v2.4s, v2.4s
204 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
205 ; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s
206 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
207 ; CHECK-NEXT:    movi v1.4s, #1
208 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
209 ; CHECK-NEXT:    ret
210   %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5>
211   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
212   %ret = zext <4 x i1> %cmp to <4 x i32>
213   ret <4 x i32> %ret
216 ; One power-of-two divisor in even divisor
217 define <4 x i32> @test_urem_even_poweroftwo(<4 x i32> %X) nounwind {
218 ; CHECK-LABEL: test_urem_even_poweroftwo:
220 ; CHECK-NEXT:    adrp x8, .LCPI8_0
221 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI8_0]
222 ; CHECK-NEXT:    adrp x8, .LCPI8_1
223 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI8_1]
224 ; CHECK-NEXT:    adrp x8, .LCPI8_2
225 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI8_2]
226 ; CHECK-NEXT:    neg v1.4s, v1.4s
227 ; CHECK-NEXT:    adrp x8, .LCPI8_3
228 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
229 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
230 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
231 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI8_3]
232 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
233 ; CHECK-NEXT:    neg v3.4s, v3.4s
234 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
235 ; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
236 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
237 ; CHECK-NEXT:    movi v1.4s, #1
238 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
239 ; CHECK-NEXT:    ret
240   %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14>
241   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
242   %ret = zext <4 x i1> %cmp to <4 x i32>
243   ret <4 x i32> %ret
246 ; One power-of-two divisor in odd+even divisor
247 define <4 x i32> @test_urem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
248 ; CHECK-LABEL: test_urem_odd_even_poweroftwo:
250 ; CHECK-NEXT:    adrp x8, .LCPI9_0
251 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI9_0]
252 ; CHECK-NEXT:    adrp x8, .LCPI9_1
253 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI9_1]
254 ; CHECK-NEXT:    adrp x8, .LCPI9_2
255 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI9_2]
256 ; CHECK-NEXT:    neg v1.4s, v1.4s
257 ; CHECK-NEXT:    adrp x8, .LCPI9_3
258 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
259 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
260 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
261 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI9_3]
262 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
263 ; CHECK-NEXT:    neg v3.4s, v3.4s
264 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
265 ; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
266 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
267 ; CHECK-NEXT:    movi v1.4s, #1
268 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
269 ; CHECK-NEXT:    ret
270   %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100>
271   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
272   %ret = zext <4 x i1> %cmp to <4 x i32>
273   ret <4 x i32> %ret
276 ;------------------------------------------------------------------------------;
279 define <4 x i32> @test_urem_odd_one(<4 x i32> %X) nounwind {
280 ; CHECK-LABEL: test_urem_odd_one:
282 ; CHECK-NEXT:    adrp x8, .LCPI10_0
283 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI10_0]
284 ; CHECK-NEXT:    mov w8, #52429
285 ; CHECK-NEXT:    movk w8, #52428, lsl #16
286 ; CHECK-NEXT:    dup v2.4s, w8
287 ; CHECK-NEXT:    mul v0.4s, v0.4s, v2.4s
288 ; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
289 ; CHECK-NEXT:    movi v1.4s, #1
290 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
291 ; CHECK-NEXT:    ret
292   %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 1, i32 5>
293   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
294   %ret = zext <4 x i1> %cmp to <4 x i32>
295   ret <4 x i32> %ret
299 define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
300 ; CHECK-LABEL: test_urem_even_one:
302 ; CHECK-NEXT:    adrp x8, .LCPI11_0
303 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI11_0]
304 ; CHECK-NEXT:    adrp x8, .LCPI11_1
305 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI11_1]
306 ; CHECK-NEXT:    adrp x8, .LCPI11_2
307 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI11_2]
308 ; CHECK-NEXT:    neg v1.4s, v1.4s
309 ; CHECK-NEXT:    adrp x8, .LCPI11_3
310 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
311 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
312 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
313 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI11_3]
314 ; CHECK-NEXT:    adrp x8, .LCPI11_4
315 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
316 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI11_4]
317 ; CHECK-NEXT:    neg v3.4s, v3.4s
318 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
319 ; CHECK-NEXT:    bit v1.16b, v0.16b, v2.16b
320 ; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
321 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
322 ; CHECK-NEXT:    movi v1.4s, #1
323 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
324 ; CHECK-NEXT:    ret
325   %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
326   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
327   %ret = zext <4 x i1> %cmp to <4 x i32>
328   ret <4 x i32> %ret
332 define <4 x i32> @test_urem_odd_even_one(<4 x i32> %X) nounwind {
333 ; CHECK-LABEL: test_urem_odd_even_one:
335 ; CHECK-NEXT:    adrp x8, .LCPI12_0
336 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI12_0]
337 ; CHECK-NEXT:    adrp x8, .LCPI12_1
338 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI12_1]
339 ; CHECK-NEXT:    adrp x8, .LCPI12_2
340 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI12_2]
341 ; CHECK-NEXT:    neg v1.4s, v1.4s
342 ; CHECK-NEXT:    adrp x8, .LCPI12_3
343 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
344 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
345 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
346 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI12_3]
347 ; CHECK-NEXT:    adrp x8, .LCPI12_4
348 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
349 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI12_4]
350 ; CHECK-NEXT:    neg v3.4s, v3.4s
351 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
352 ; CHECK-NEXT:    bit v1.16b, v0.16b, v2.16b
353 ; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
354 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
355 ; CHECK-NEXT:    movi v1.4s, #1
356 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
357 ; CHECK-NEXT:    ret
358   %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100>
359   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
360   %ret = zext <4 x i1> %cmp to <4 x i32>
361   ret <4 x i32> %ret
364 ;------------------------------------------------------------------------------;
367 define <4 x i32> @test_urem_odd_INT_MIN(<4 x i32> %X) nounwind {
368 ; CHECK-LABEL: test_urem_odd_INT_MIN:
370 ; CHECK-NEXT:    adrp x8, .LCPI13_0
371 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI13_0]
372 ; CHECK-NEXT:    adrp x8, .LCPI13_1
373 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI13_1]
374 ; CHECK-NEXT:    adrp x8, .LCPI13_2
375 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI13_2]
376 ; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
377 ; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
378 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
379 ; CHECK-NEXT:    neg v2.4s, v2.4s
380 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
381 ; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s
382 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
383 ; CHECK-NEXT:    movi v1.4s, #1
384 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
385 ; CHECK-NEXT:    ret
386   %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5>
387   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
388   %ret = zext <4 x i1> %cmp to <4 x i32>
389   ret <4 x i32> %ret
393 define <4 x i32> @test_urem_even_INT_MIN(<4 x i32> %X) nounwind {
394 ; CHECK-LABEL: test_urem_even_INT_MIN:
396 ; CHECK-NEXT:    adrp x8, .LCPI14_0
397 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_0]
398 ; CHECK-NEXT:    adrp x8, .LCPI14_1
399 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI14_1]
400 ; CHECK-NEXT:    adrp x8, .LCPI14_2
401 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI14_2]
402 ; CHECK-NEXT:    neg v1.4s, v1.4s
403 ; CHECK-NEXT:    adrp x8, .LCPI14_3
404 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
405 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
406 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
407 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI14_3]
408 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
409 ; CHECK-NEXT:    neg v3.4s, v3.4s
410 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
411 ; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
412 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
413 ; CHECK-NEXT:    movi v1.4s, #1
414 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
415 ; CHECK-NEXT:    ret
416   %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14>
417   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
418   %ret = zext <4 x i1> %cmp to <4 x i32>
419   ret <4 x i32> %ret
423 define <4 x i32> @test_urem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
424 ; CHECK-LABEL: test_urem_odd_even_INT_MIN:
426 ; CHECK-NEXT:    adrp x8, .LCPI15_0
427 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI15_0]
428 ; CHECK-NEXT:    adrp x8, .LCPI15_1
429 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI15_1]
430 ; CHECK-NEXT:    adrp x8, .LCPI15_2
431 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI15_2]
432 ; CHECK-NEXT:    neg v1.4s, v1.4s
433 ; CHECK-NEXT:    adrp x8, .LCPI15_3
434 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
435 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
436 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
437 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI15_3]
438 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
439 ; CHECK-NEXT:    neg v3.4s, v3.4s
440 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
441 ; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
442 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
443 ; CHECK-NEXT:    movi v1.4s, #1
444 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
445 ; CHECK-NEXT:    ret
446   %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100>
447   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
448   %ret = zext <4 x i1> %cmp to <4 x i32>
449   ret <4 x i32> %ret
454 ; One all-ones divisor and power-of-two divisor divisor in odd divisor
455 define <4 x i32> @test_urem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
456 ; CHECK-LABEL: test_urem_odd_allones_and_poweroftwo:
458 ; CHECK-NEXT:    adrp x8, .LCPI16_0
459 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_0]
460 ; CHECK-NEXT:    adrp x8, .LCPI16_1
461 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI16_1]
462 ; CHECK-NEXT:    adrp x8, .LCPI16_2
463 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI16_2]
464 ; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
465 ; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
466 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
467 ; CHECK-NEXT:    neg v2.4s, v2.4s
468 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
469 ; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s
470 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
471 ; CHECK-NEXT:    movi v1.4s, #1
472 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
473 ; CHECK-NEXT:    ret
474   %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5>
475   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
476   %ret = zext <4 x i1> %cmp to <4 x i32>
477   ret <4 x i32> %ret
480 ; One all-ones divisor and power-of-two divisor divisor in even divisor
481 define <4 x i32> @test_urem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
482 ; CHECK-LABEL: test_urem_even_allones_and_poweroftwo:
484 ; CHECK-NEXT:    adrp x8, .LCPI17_0
485 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_0]
486 ; CHECK-NEXT:    adrp x8, .LCPI17_1
487 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI17_1]
488 ; CHECK-NEXT:    adrp x8, .LCPI17_2
489 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI17_2]
490 ; CHECK-NEXT:    neg v1.4s, v1.4s
491 ; CHECK-NEXT:    adrp x8, .LCPI17_3
492 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
493 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
494 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
495 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI17_3]
496 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
497 ; CHECK-NEXT:    neg v3.4s, v3.4s
498 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
499 ; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
500 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
501 ; CHECK-NEXT:    movi v1.4s, #1
502 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
503 ; CHECK-NEXT:    ret
504   %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14>
505   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
506   %ret = zext <4 x i1> %cmp to <4 x i32>
507   ret <4 x i32> %ret
510 ; One all-ones divisor and power-of-two divisor divisor in odd+even divisor
511 define <4 x i32> @test_urem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
512 ; CHECK-LABEL: test_urem_odd_even_allones_and_poweroftwo:
514 ; CHECK-NEXT:    adrp x8, .LCPI18_0
515 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI18_0]
516 ; CHECK-NEXT:    adrp x8, .LCPI18_1
517 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI18_1]
518 ; CHECK-NEXT:    adrp x8, .LCPI18_2
519 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI18_2]
520 ; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
521 ; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
522 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
523 ; CHECK-NEXT:    neg v2.4s, v2.4s
524 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
525 ; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s
526 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
527 ; CHECK-NEXT:    movi v1.4s, #1
528 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
529 ; CHECK-NEXT:    ret
530   %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100>
531   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
532   %ret = zext <4 x i1> %cmp to <4 x i32>
533   ret <4 x i32> %ret
536 ;------------------------------------------------------------------------------;
538 ; One all-ones divisor and one one divisor in odd divisor
539 define <4 x i32> @test_urem_odd_allones_and_one(<4 x i32> %X) nounwind {
540 ; CHECK-LABEL: test_urem_odd_allones_and_one:
542 ; CHECK-NEXT:    adrp x8, .LCPI19_0
543 ; CHECK-NEXT:    adrp x9, .LCPI19_1
544 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI19_0]
545 ; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI19_1]
546 ; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
547 ; CHECK-NEXT:    cmhs v0.4s, v2.4s, v0.4s
548 ; CHECK-NEXT:    movi v1.4s, #1
549 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
550 ; CHECK-NEXT:    ret
551   %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 5>
552   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
553   %ret = zext <4 x i1> %cmp to <4 x i32>
554   ret <4 x i32> %ret
557 ; One all-ones divisor and one one divisor in even divisor
558 define <4 x i32> @test_urem_even_allones_and_one(<4 x i32> %X) nounwind {
559 ; CHECK-LABEL: test_urem_even_allones_and_one:
561 ; CHECK-NEXT:    adrp x8, .LCPI20_0
562 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI20_0]
563 ; CHECK-NEXT:    adrp x8, .LCPI20_1
564 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI20_1]
565 ; CHECK-NEXT:    adrp x8, .LCPI20_2
566 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI20_2]
567 ; CHECK-NEXT:    neg v1.4s, v1.4s
568 ; CHECK-NEXT:    adrp x8, .LCPI20_3
569 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
570 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
571 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
572 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI20_3]
573 ; CHECK-NEXT:    adrp x8, .LCPI20_4
574 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
575 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI20_4]
576 ; CHECK-NEXT:    neg v3.4s, v3.4s
577 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
578 ; CHECK-NEXT:    bit v1.16b, v0.16b, v2.16b
579 ; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
580 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
581 ; CHECK-NEXT:    movi v1.4s, #1
582 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
583 ; CHECK-NEXT:    ret
584   %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>
585   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
586   %ret = zext <4 x i1> %cmp to <4 x i32>
587   ret <4 x i32> %ret
590 ; One all-ones divisor and one one divisor in odd+even divisor
591 define <4 x i32> @test_urem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
592 ; CHECK-LABEL: test_urem_odd_even_allones_and_one:
594 ; CHECK-NEXT:    adrp x8, .LCPI21_0
595 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI21_0]
596 ; CHECK-NEXT:    adrp x8, .LCPI21_1
597 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI21_1]
598 ; CHECK-NEXT:    adrp x8, .LCPI21_2
599 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI21_2]
600 ; CHECK-NEXT:    adrp x8, .LCPI21_3
601 ; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
602 ; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
603 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
604 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI21_3]
605 ; CHECK-NEXT:    neg v2.4s, v2.4s
606 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
607 ; CHECK-NEXT:    bit v1.16b, v0.16b, v3.16b
608 ; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
609 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
610 ; CHECK-NEXT:    movi v1.4s, #1
611 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
612 ; CHECK-NEXT:    ret
613   %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100>
614   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
615   %ret = zext <4 x i1> %cmp to <4 x i32>
616   ret <4 x i32> %ret
619 ;------------------------------------------------------------------------------;
621 ; One power-of-two divisor divisor and one divisor in odd divisor
622 define <4 x i32> @test_urem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
623 ; CHECK-LABEL: test_urem_odd_poweroftwo_and_one:
625 ; CHECK-NEXT:    adrp x8, .LCPI22_0
626 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI22_0]
627 ; CHECK-NEXT:    adrp x8, .LCPI22_1
628 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI22_1]
629 ; CHECK-NEXT:    adrp x8, .LCPI22_2
630 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI22_2]
631 ; CHECK-NEXT:    adrp x8, .LCPI22_3
632 ; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
633 ; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
634 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
635 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI22_3]
636 ; CHECK-NEXT:    neg v2.4s, v2.4s
637 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
638 ; CHECK-NEXT:    bit v1.16b, v0.16b, v3.16b
639 ; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
640 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
641 ; CHECK-NEXT:    movi v1.4s, #1
642 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
643 ; CHECK-NEXT:    ret
644   %urem = urem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5>
645   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
646   %ret = zext <4 x i1> %cmp to <4 x i32>
647   ret <4 x i32> %ret
650 ; One power-of-two divisor divisor and one divisor in even divisor
651 define <4 x i32> @test_urem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
652 ; CHECK-LABEL: test_urem_even_poweroftwo_and_one:
654 ; CHECK-NEXT:    adrp x8, .LCPI23_0
655 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI23_0]
656 ; CHECK-NEXT:    adrp x8, .LCPI23_1
657 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI23_1]
658 ; CHECK-NEXT:    adrp x8, .LCPI23_2
659 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI23_2]
660 ; CHECK-NEXT:    neg v1.4s, v1.4s
661 ; CHECK-NEXT:    adrp x8, .LCPI23_3
662 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
663 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
664 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
665 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI23_3]
666 ; CHECK-NEXT:    adrp x8, .LCPI23_4
667 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
668 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI23_4]
669 ; CHECK-NEXT:    neg v3.4s, v3.4s
670 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
671 ; CHECK-NEXT:    bit v1.16b, v0.16b, v2.16b
672 ; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
673 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
674 ; CHECK-NEXT:    movi v1.4s, #1
675 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
676 ; CHECK-NEXT:    ret
677   %urem = urem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14>
678   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
679   %ret = zext <4 x i1> %cmp to <4 x i32>
680   ret <4 x i32> %ret
683 ; One power-of-two divisor divisor and one divisor in odd+even divisor
684 define <4 x i32> @test_urem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
685 ; CHECK-LABEL: test_urem_odd_even_poweroftwo_and_one:
687 ; CHECK-NEXT:    adrp x8, .LCPI24_0
688 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI24_0]
689 ; CHECK-NEXT:    adrp x8, .LCPI24_1
690 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI24_1]
691 ; CHECK-NEXT:    adrp x8, .LCPI24_2
692 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI24_2]
693 ; CHECK-NEXT:    adrp x8, .LCPI24_3
694 ; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
695 ; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
696 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
697 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI24_3]
698 ; CHECK-NEXT:    neg v2.4s, v2.4s
699 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
700 ; CHECK-NEXT:    bit v1.16b, v0.16b, v3.16b
701 ; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
702 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
703 ; CHECK-NEXT:    movi v1.4s, #1
704 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
705 ; CHECK-NEXT:    ret
706   %urem = urem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100>
707   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
708   %ret = zext <4 x i1> %cmp to <4 x i32>
709   ret <4 x i32> %ret
712 ;------------------------------------------------------------------------------;
714 define <4 x i32> @test_urem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
715 ; CHECK-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
717 ; CHECK-NEXT:    adrp x8, .LCPI25_0
718 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI25_0]
719 ; CHECK-NEXT:    adrp x8, .LCPI25_1
720 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI25_1]
721 ; CHECK-NEXT:    adrp x8, .LCPI25_2
722 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI25_2]
723 ; CHECK-NEXT:    adrp x8, .LCPI25_3
724 ; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
725 ; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
726 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
727 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI25_3]
728 ; CHECK-NEXT:    neg v2.4s, v2.4s
729 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
730 ; CHECK-NEXT:    bit v1.16b, v0.16b, v3.16b
731 ; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
732 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
733 ; CHECK-NEXT:    movi v1.4s, #1
734 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
735 ; CHECK-NEXT:    ret
736   %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1>
737   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
738   %ret = zext <4 x i1> %cmp to <4 x i32>
739   ret <4 x i32> %ret
742 define <4 x i32> @test_urem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
743 ; CHECK-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
745 ; CHECK-NEXT:    adrp x8, .LCPI26_0
746 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI26_0]
747 ; CHECK-NEXT:    adrp x8, .LCPI26_1
748 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI26_1]
749 ; CHECK-NEXT:    adrp x8, .LCPI26_2
750 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI26_2]
751 ; CHECK-NEXT:    neg v1.4s, v1.4s
752 ; CHECK-NEXT:    adrp x8, .LCPI26_3
753 ; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
754 ; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
755 ; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
756 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI26_3]
757 ; CHECK-NEXT:    adrp x8, .LCPI26_4
758 ; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
759 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI26_4]
760 ; CHECK-NEXT:    neg v3.4s, v3.4s
761 ; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
762 ; CHECK-NEXT:    bit v1.16b, v0.16b, v2.16b
763 ; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
764 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
765 ; CHECK-NEXT:    movi v1.4s, #1
766 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
767 ; CHECK-NEXT:    ret
768   %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1>
769   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
770   %ret = zext <4 x i1> %cmp to <4 x i32>
771   ret <4 x i32> %ret