Lines Matching refs:MIR
7 …struction-select -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX8-MIR %s
8 …struction-select -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9-MIR %s
28 ; GFX8-MIR-LABEL: name: ds_fmax_f32_ss
29 ; GFX8-MIR: bb.1 (%ir-block.0):
30 ; GFX8-MIR: liveins: $sgpr2, $sgpr3
31 ; GFX8-MIR: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
32 ; GFX8-MIR: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
33 ; GFX8-MIR: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
34 ; GFX8-MIR: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
35 ; GFX8-MIR: $m0 = S_MOV_B32 -1
36 …; GFX8-MIR: [[DS_MAX_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32 [[COPY2]], [[COPY3]], 0, 0, imp…
37 ; GFX8-MIR: $vgpr0 = COPY [[DS_MAX_RTN_F32_]]
38 ; GFX8-MIR: SI_RETURN_TO_EPILOG implicit $vgpr0
39 ; GFX9-MIR-LABEL: name: ds_fmax_f32_ss
40 ; GFX9-MIR: bb.1 (%ir-block.0):
41 ; GFX9-MIR: liveins: $sgpr2, $sgpr3
42 ; GFX9-MIR: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
43 ; GFX9-MIR: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
44 ; GFX9-MIR: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
45 ; GFX9-MIR: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
46 …; GFX9-MIR: [[DS_MAX_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32_gfx9 [[COPY2]], [[COPY3]],…
47 ; GFX9-MIR: $vgpr0 = COPY [[DS_MAX_RTN_F32_gfx9_]]
48 ; GFX9-MIR: SI_RETURN_TO_EPILOG implicit $vgpr0
70 ; GFX8-MIR-LABEL: name: ds_fmax_f32_ss_offset
71 ; GFX8-MIR: bb.1 (%ir-block.0):
72 ; GFX8-MIR: liveins: $sgpr2, $sgpr3
73 ; GFX8-MIR: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
74 ; GFX8-MIR: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
75 ; GFX8-MIR: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
76 ; GFX8-MIR: $m0 = S_MOV_B32 -1
77 ; GFX8-MIR: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
78 …; GFX8-MIR: [[DS_MAX_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32 [[COPY3]], [[COPY2]], 512, 0, i…
79 ; GFX8-MIR: $vgpr0 = COPY [[DS_MAX_RTN_F32_]]
80 ; GFX8-MIR: SI_RETURN_TO_EPILOG implicit $vgpr0
81 ; GFX9-MIR-LABEL: name: ds_fmax_f32_ss_offset
82 ; GFX9-MIR: bb.1 (%ir-block.0):
83 ; GFX9-MIR: liveins: $sgpr2, $sgpr3
84 ; GFX9-MIR: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
85 ; GFX9-MIR: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
86 ; GFX9-MIR: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
87 ; GFX9-MIR: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
88 …; GFX9-MIR: [[DS_MAX_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32_gfx9 [[COPY3]], [[COPY2]],…
89 ; GFX9-MIR: $vgpr0 = COPY [[DS_MAX_RTN_F32_gfx9_]]
90 ; GFX9-MIR: SI_RETURN_TO_EPILOG implicit $vgpr0
111 ; GFX8-MIR-LABEL: name: ds_fmax_f32_ss_nortn
112 ; GFX8-MIR: bb.1 (%ir-block.0):
113 ; GFX8-MIR: liveins: $sgpr2, $sgpr3
114 ; GFX8-MIR: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
115 ; GFX8-MIR: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
116 ; GFX8-MIR: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
117 ; GFX8-MIR: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
118 ; GFX8-MIR: $m0 = S_MOV_B32 -1
119 …; GFX8-MIR: [[DS_MAX_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32 [[COPY2]], [[COPY3]], 0, 0, imp…
120 ; GFX8-MIR: S_ENDPGM 0
121 ; GFX9-MIR-LABEL: name: ds_fmax_f32_ss_nortn
122 ; GFX9-MIR: bb.1 (%ir-block.0):
123 ; GFX9-MIR: liveins: $sgpr2, $sgpr3
124 ; GFX9-MIR: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
125 ; GFX9-MIR: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
126 ; GFX9-MIR: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
127 ; GFX9-MIR: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
128 …; GFX9-MIR: [[DS_MAX_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32_gfx9 [[COPY2]], [[COPY3]],…
129 ; GFX9-MIR: S_ENDPGM 0
149 ; GFX8-MIR-LABEL: name: ds_fmax_f32_ss_offset_nortn
150 ; GFX8-MIR: bb.1 (%ir-block.0):
151 ; GFX8-MIR: liveins: $sgpr2, $sgpr3
152 ; GFX8-MIR: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
153 ; GFX8-MIR: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
154 ; GFX8-MIR: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
155 ; GFX8-MIR: $m0 = S_MOV_B32 -1
156 ; GFX8-MIR: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
157 …; GFX8-MIR: [[DS_MAX_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32 [[COPY3]], [[COPY2]], 512, 0, i…
158 ; GFX8-MIR: S_ENDPGM 0
159 ; GFX9-MIR-LABEL: name: ds_fmax_f32_ss_offset_nortn
160 ; GFX9-MIR: bb.1 (%ir-block.0):
161 ; GFX9-MIR: liveins: $sgpr2, $sgpr3
162 ; GFX9-MIR: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
163 ; GFX9-MIR: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
164 ; GFX9-MIR: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
165 ; GFX9-MIR: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
166 …; GFX9-MIR: [[DS_MAX_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32_gfx9 [[COPY3]], [[COPY2]],…
167 ; GFX9-MIR: S_ENDPGM 0
188 ; GFX8-MIR-LABEL: name: ds_fmax_f32_vv
189 ; GFX8-MIR: bb.1 (%ir-block.0):
190 ; GFX8-MIR: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
191 ; GFX8-MIR: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
192 ; GFX8-MIR: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
193 ; GFX8-MIR: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
194 ; GFX8-MIR: $m0 = S_MOV_B32 -1
195 …; GFX8-MIR: [[DS_MAX_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32 [[COPY]], [[COPY1]], 0, 0, impl…
196 ; GFX8-MIR: $vgpr0 = COPY [[DS_MAX_RTN_F32_]]
197 ; GFX8-MIR: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
198 ; GFX8-MIR: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
199 ; GFX9-MIR-LABEL: name: ds_fmax_f32_vv
200 ; GFX9-MIR: bb.1 (%ir-block.0):
201 ; GFX9-MIR: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
202 ; GFX9-MIR: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
203 ; GFX9-MIR: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
204 ; GFX9-MIR: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
205 …; GFX9-MIR: [[DS_MAX_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32_gfx9 [[COPY]], [[COPY1]], …
206 ; GFX9-MIR: $vgpr0 = COPY [[DS_MAX_RTN_F32_gfx9_]]
207 ; GFX9-MIR: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
208 ; GFX9-MIR: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
228 ; GFX8-MIR-LABEL: name: ds_fmax_f32_vv_offset
229 ; GFX8-MIR: bb.1 (%ir-block.0):
230 ; GFX8-MIR: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
231 ; GFX8-MIR: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
232 ; GFX8-MIR: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
233 ; GFX8-MIR: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
234 ; GFX8-MIR: $m0 = S_MOV_B32 -1
235 …; GFX8-MIR: [[DS_MAX_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32 [[COPY]], [[COPY1]], 512, 0, im…
236 ; GFX8-MIR: $vgpr0 = COPY [[DS_MAX_RTN_F32_]]
237 ; GFX8-MIR: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
238 ; GFX8-MIR: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
239 ; GFX9-MIR-LABEL: name: ds_fmax_f32_vv_offset
240 ; GFX9-MIR: bb.1 (%ir-block.0):
241 ; GFX9-MIR: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
242 ; GFX9-MIR: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
243 ; GFX9-MIR: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
244 ; GFX9-MIR: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
245 …; GFX9-MIR: [[DS_MAX_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32_gfx9 [[COPY]], [[COPY1]], …
246 ; GFX9-MIR: $vgpr0 = COPY [[DS_MAX_RTN_F32_gfx9_]]
247 ; GFX9-MIR: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
248 ; GFX9-MIR: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
269 ; GFX8-MIR-LABEL: name: ds_fmax_f32_vv_nortn
270 ; GFX8-MIR: bb.1 (%ir-block.0):
271 ; GFX8-MIR: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
272 ; GFX8-MIR: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
273 ; GFX8-MIR: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
274 ; GFX8-MIR: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
275 ; GFX8-MIR: $m0 = S_MOV_B32 -1
276 …; GFX8-MIR: [[DS_MAX_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32 [[COPY]], [[COPY1]], 0, 0, impl…
277 ; GFX8-MIR: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
278 ; GFX8-MIR: S_SETPC_B64_return [[COPY3]]
279 ; GFX9-MIR-LABEL: name: ds_fmax_f32_vv_nortn
280 ; GFX9-MIR: bb.1 (%ir-block.0):
281 ; GFX9-MIR: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
282 ; GFX9-MIR: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
283 ; GFX9-MIR: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
284 ; GFX9-MIR: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
285 …; GFX9-MIR: [[DS_MAX_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32_gfx9 [[COPY]], [[COPY1]], …
286 ; GFX9-MIR: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
287 ; GFX9-MIR: S_SETPC_B64_return [[COPY3]]
307 ; GFX8-MIR-LABEL: name: ds_fmax_f32_vv_offset_nortn
308 ; GFX8-MIR: bb.1 (%ir-block.0):
309 ; GFX8-MIR: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
310 ; GFX8-MIR: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
311 ; GFX8-MIR: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
312 ; GFX8-MIR: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
313 ; GFX8-MIR: $m0 = S_MOV_B32 -1
314 …; GFX8-MIR: [[DS_MAX_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32 [[COPY]], [[COPY1]], 512, 0, im…
315 ; GFX8-MIR: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
316 ; GFX8-MIR: S_SETPC_B64_return [[COPY3]]
317 ; GFX9-MIR-LABEL: name: ds_fmax_f32_vv_offset_nortn
318 ; GFX9-MIR: bb.1 (%ir-block.0):
319 ; GFX9-MIR: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
320 ; GFX9-MIR: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
321 ; GFX9-MIR: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
322 ; GFX9-MIR: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
323 …; GFX9-MIR: [[DS_MAX_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32_gfx9 [[COPY]], [[COPY1]], …
324 ; GFX9-MIR: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
325 ; GFX9-MIR: S_SETPC_B64_return [[COPY3]]
346 ; GFX8-MIR-LABEL: name: ds_fmax_f32_vv_volatile
347 ; GFX8-MIR: bb.1 (%ir-block.0):
348 ; GFX8-MIR: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
349 ; GFX8-MIR: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
350 ; GFX8-MIR: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
351 ; GFX8-MIR: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
352 ; GFX8-MIR: $m0 = S_MOV_B32 -1
353 …; GFX8-MIR: [[DS_MAX_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32 [[COPY]], [[COPY1]], 0, 0, impl…
354 ; GFX8-MIR: $vgpr0 = COPY [[DS_MAX_RTN_F32_]]
355 ; GFX8-MIR: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
356 ; GFX8-MIR: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
357 ; GFX9-MIR-LABEL: name: ds_fmax_f32_vv_volatile
358 ; GFX9-MIR: bb.1 (%ir-block.0):
359 ; GFX9-MIR: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
360 ; GFX9-MIR: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
361 ; GFX9-MIR: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
362 ; GFX9-MIR: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
363 …; GFX9-MIR: [[DS_MAX_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32_gfx9 [[COPY]], [[COPY1]], …
364 ; GFX9-MIR: $vgpr0 = COPY [[DS_MAX_RTN_F32_gfx9_]]
365 ; GFX9-MIR: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
366 ; GFX9-MIR: S_SETPC_B64_return [[COPY3]], implicit $vgpr0