Lines Matching refs:s17
788 ; GFX7-NEXT: s_mul_i32 s17, s1, s8
790 ; GFX7-NEXT: s_add_u32 s17, s17, s18
792 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s17, v0
796 ; GFX7-NEXT: s_mul_i32 s17, s2, s8
799 ; GFX7-NEXT: s_add_u32 s17, s17, s18
804 ; GFX7-NEXT: s_add_u32 s17, s17, s19
808 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, s17, v2
814 ; GFX7-NEXT: s_mul_i32 s17, s3, s8
817 ; GFX7-NEXT: s_add_u32 s17, s17, s18
824 ; GFX7-NEXT: s_add_u32 s17, s17, s19
832 ; GFX7-NEXT: s_add_u32 s17, s17, s20
835 ; GFX7-NEXT: v_add_i32_e32 v5, vcc, s17, v5
842 ; GFX7-NEXT: s_mul_i32 s17, s4, s8
845 ; GFX7-NEXT: s_add_u32 s17, s17, s18
852 ; GFX7-NEXT: s_add_u32 s17, s17, s19
861 ; GFX7-NEXT: s_add_u32 s17, s17, s20
869 ; GFX7-NEXT: s_add_u32 s17, s17, s21
871 ; GFX7-NEXT: v_add_i32_e32 v7, vcc, s17, v7
877 ; GFX7-NEXT: s_mul_i32 s17, s5, s8
879 ; GFX7-NEXT: s_add_u32 s17, s17, s18
888 ; GFX7-NEXT: s_add_u32 s17, s17, s19
898 ; GFX7-NEXT: s_add_u32 s17, s17, s20
907 ; GFX7-NEXT: s_add_u32 s17, s17, s21
915 ; GFX7-NEXT: s_add_u32 s17, s17, s22
917 ; GFX7-NEXT: v_add_i32_e32 v8, vcc, s17, v8
923 ; GFX7-NEXT: s_mul_i32 s17, s6, s8
925 ; GFX7-NEXT: s_add_u32 s17, s17, s18
932 ; GFX7-NEXT: s_add_u32 s17, s17, s19
943 ; GFX7-NEXT: s_add_u32 s17, s17, s20
953 ; GFX7-NEXT: s_add_u32 s17, s17, s21
962 ; GFX7-NEXT: s_add_u32 s17, s17, s22
970 ; GFX7-NEXT: s_add_u32 s17, s17, s23
973 ; GFX7-NEXT: v_add_i32_e32 v10, vcc, s17, v10
1000 ; GFX7-NEXT: s_mul_i32 s17, s6, s9
1006 ; GFX7-NEXT: s_add_i32 s0, s7, s17
1048 ; GFX8-NEXT: s_mul_i32 s17, s1, s8
1050 ; GFX8-NEXT: s_add_u32 s17, s17, s18
1052 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s17, v0
1056 ; GFX8-NEXT: s_mul_i32 s17, s2, s8
1059 ; GFX8-NEXT: s_add_u32 s17, s17, s18
1064 ; GFX8-NEXT: s_add_u32 s17, s17, s19
1068 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, s17, v2
1074 ; GFX8-NEXT: s_mul_i32 s17, s3, s8
1077 ; GFX8-NEXT: s_add_u32 s17, s17, s18
1084 ; GFX8-NEXT: s_add_u32 s17, s17, s19
1092 ; GFX8-NEXT: s_add_u32 s17, s17, s20
1095 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, s17, v5
1102 ; GFX8-NEXT: s_mul_i32 s17, s4, s8
1105 ; GFX8-NEXT: s_add_u32 s17, s17, s18
1112 ; GFX8-NEXT: s_add_u32 s17, s17, s19
1121 ; GFX8-NEXT: s_add_u32 s17, s17, s20
1129 ; GFX8-NEXT: s_add_u32 s17, s17, s21
1131 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, s17, v7
1137 ; GFX8-NEXT: s_mul_i32 s17, s5, s8
1139 ; GFX8-NEXT: s_add_u32 s17, s17, s18
1148 ; GFX8-NEXT: s_add_u32 s17, s17, s19
1158 ; GFX8-NEXT: s_add_u32 s17, s17, s20
1167 ; GFX8-NEXT: s_add_u32 s17, s17, s21
1175 ; GFX8-NEXT: s_add_u32 s17, s17, s22
1177 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, s17, v8
1183 ; GFX8-NEXT: s_mul_i32 s17, s6, s8
1185 ; GFX8-NEXT: s_add_u32 s17, s17, s18
1192 ; GFX8-NEXT: s_add_u32 s17, s17, s19
1203 ; GFX8-NEXT: s_add_u32 s17, s17, s20
1213 ; GFX8-NEXT: s_add_u32 s17, s17, s21
1222 ; GFX8-NEXT: s_add_u32 s17, s17, s22
1230 ; GFX8-NEXT: s_add_u32 s17, s17, s23
1233 ; GFX8-NEXT: v_add_u32_e32 v10, vcc, s17, v10
1260 ; GFX8-NEXT: s_mul_i32 s17, s6, s9
1266 ; GFX8-NEXT: s_add_i32 s0, s7, s17
1306 ; GFX9-NEXT: s_mul_i32 s17, s1, s8
1308 ; GFX9-NEXT: s_add_u32 s17, s17, s18
1312 ; GFX9-NEXT: s_add_u32 s17, s17, s19
1568 ; GFX9-NEXT: s_mov_b32 s1, s17