Lines Matching refs:GFX1010

4 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX1010 %s
15 ; GFX1010-LABEL: test_kern_empty:
16 ; GFX1010:       ; %bb.0: ; %entry
17 ; GFX1010-NEXT:    s_endpgm
44 ; GFX1010-LABEL: test_kern_stack:
45 ; GFX1010:       ; %bb.0: ; %entry
46 ; GFX1010-NEXT:    s_add_u32 s4, s4, s7
47 ; GFX1010-NEXT:    s_addc_u32 s5, s5, 0
48 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
49 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
50 ; GFX1010-NEXT:    v_mov_b32_e32 v0, 0
51 ; GFX1010-NEXT:    s_add_u32 s0, s0, s7
52 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
53 ; GFX1010-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
54 ; GFX1010-NEXT:    s_endpgm
89 ; GFX1010-LABEL: test_kern_call:
90 ; GFX1010:       ; %bb.0: ; %entry
91 ; GFX1010-NEXT:    s_add_u32 s4, s4, s7
92 ; GFX1010-NEXT:    s_mov_b32 s32, 0
93 ; GFX1010-NEXT:    s_addc_u32 s5, s5, 0
94 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
95 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
96 ; GFX1010-NEXT:    s_add_u32 s0, s0, s7
97 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
98 ; GFX1010-NEXT:    s_getpc_b64 s[4:5]
99 ; GFX1010-NEXT:    s_add_u32 s4, s4, ex@rel32@lo+4
100 ; GFX1010-NEXT:    s_addc_u32 s5, s5, ex@rel32@hi+12
101 ; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[4:5]
102 ; GFX1010-NEXT:    s_endpgm
140 ; GFX1010-LABEL: test_kern_stack_and_call:
141 ; GFX1010:       ; %bb.0: ; %entry
142 ; GFX1010-NEXT:    s_add_u32 s4, s4, s7
143 ; GFX1010-NEXT:    s_movk_i32 s32, 0x200
144 ; GFX1010-NEXT:    s_addc_u32 s5, s5, 0
145 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
146 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
147 ; GFX1010-NEXT:    v_mov_b32_e32 v0, 0
148 ; GFX1010-NEXT:    s_add_u32 s0, s0, s7
149 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
150 ; GFX1010-NEXT:    s_getpc_b64 s[4:5]
151 ; GFX1010-NEXT:    s_add_u32 s4, s4, ex@rel32@lo+4
152 ; GFX1010-NEXT:    s_addc_u32 s5, s5, ex@rel32@hi+12
153 ; GFX1010-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
154 ; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[4:5]
155 ; GFX1010-NEXT:    s_endpgm
174 ; GFX1010-LABEL: test_force_fp_kern_empty:
175 ; GFX1010:       ; %bb.0: ; %entry
176 ; GFX1010-NEXT:    s_mov_b32 s33, 0
177 ; GFX1010-NEXT:    s_endpgm
206 ; GFX1010-LABEL: test_force_fp_kern_stack:
207 ; GFX1010:       ; %bb.0: ; %entry
208 ; GFX1010-NEXT:    s_add_u32 s4, s4, s7
209 ; GFX1010-NEXT:    s_mov_b32 s33, 0
210 ; GFX1010-NEXT:    s_addc_u32 s5, s5, 0
211 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
212 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
213 ; GFX1010-NEXT:    v_mov_b32_e32 v0, 0
214 ; GFX1010-NEXT:    s_add_u32 s0, s0, s7
215 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
216 ; GFX1010-NEXT:    buffer_store_dword v0, off, s[0:3], s33 offset:4
217 ; GFX1010-NEXT:    s_endpgm
254 ; GFX1010-LABEL: test_force_fp_kern_call:
255 ; GFX1010:       ; %bb.0: ; %entry
256 ; GFX1010-NEXT:    s_add_u32 s4, s4, s7
257 ; GFX1010-NEXT:    s_mov_b32 s32, 0
258 ; GFX1010-NEXT:    s_mov_b32 s33, 0
259 ; GFX1010-NEXT:    s_addc_u32 s5, s5, 0
260 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
261 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
262 ; GFX1010-NEXT:    s_add_u32 s0, s0, s7
263 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
264 ; GFX1010-NEXT:    s_getpc_b64 s[4:5]
265 ; GFX1010-NEXT:    s_add_u32 s4, s4, ex@rel32@lo+4
266 ; GFX1010-NEXT:    s_addc_u32 s5, s5, ex@rel32@hi+12
267 ; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[4:5]
268 ; GFX1010-NEXT:    s_endpgm
308 ; GFX1010-LABEL: test_force_fp_kern_stack_and_call:
309 ; GFX1010:       ; %bb.0: ; %entry
310 ; GFX1010-NEXT:    s_add_u32 s4, s4, s7
311 ; GFX1010-NEXT:    s_movk_i32 s32, 0x200
312 ; GFX1010-NEXT:    s_mov_b32 s33, 0
313 ; GFX1010-NEXT:    s_addc_u32 s5, s5, 0
314 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
315 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
316 ; GFX1010-NEXT:    v_mov_b32_e32 v0, 0
317 ; GFX1010-NEXT:    s_add_u32 s0, s0, s7
318 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
319 ; GFX1010-NEXT:    s_getpc_b64 s[4:5]
320 ; GFX1010-NEXT:    s_add_u32 s4, s4, ex@rel32@lo+4
321 ; GFX1010-NEXT:    s_addc_u32 s5, s5, ex@rel32@hi+12
322 ; GFX1010-NEXT:    buffer_store_dword v0, off, s[0:3], s33 offset:4
323 ; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[4:5]
324 ; GFX1010-NEXT:    s_endpgm
370 ; GFX1010-LABEL: test_sgpr_offset_kernel:
371 ; GFX1010:       ; %bb.0: ; %entry
372 ; GFX1010-NEXT:    s_add_u32 s4, s4, s7
373 ; GFX1010-NEXT:    s_addc_u32 s5, s5, 0
374 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
375 ; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
376 ; GFX1010-NEXT:    s_add_u32 s0, s0, s7
377 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
378 ; GFX1010-NEXT:    s_mov_b32 s6, 0x20000
379 ; GFX1010-NEXT:    buffer_load_dword v0, off, s[0:3], 0 offset:8
380 ; GFX1010-NEXT:    s_waitcnt vmcnt(0)
381 ; GFX1010-NEXT:    buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
382 ; GFX1010-NEXT:    s_waitcnt_depctr 0xffe3
383 ; GFX1010-NEXT:    s_mov_b32 s6, 0x20000
384 ; GFX1010-NEXT:    ;;#ASMSTART
385 ; GFX1010-NEXT:    ;;#ASMEND
386 ; GFX1010-NEXT:    buffer_load_dword v0, off, s[0:3], s6 ; 4-byte Folded Reload
387 ; GFX1010-NEXT:    s_waitcnt vmcnt(0)
388 ; GFX1010-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:8
389 ; GFX1010-NEXT:    s_endpgm