Lines Matching +full:llvm +full:- +full:3

1 …RUN: llc < %s -march=amdgcn -mcpu=verde -amdgpu-atomic-optimizations=false -verify-machineinstrs |…
2 …RUN: llc < %s -march=amdgcn -mcpu=tonga -amdgpu-atomic-optimizations=false -verify-machineinstrs |…
4 ;CHECK-LABEL: {{^}}test1:
5 ;CHECK-NOT: s_waitcnt
6 ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc
7 ;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
9 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc
11 ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen glc
13 ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
16 ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc
17 ;CHECK-DAG: s_waitcnt vmcnt(0)
18 ;SICI: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc
19 ;VI: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:4 glc
21 ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0{{$}}
24   %o1 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
25 …%o2 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o1, <4 x i32> %rsrc, i32 %vindex, i32 0, i…
26 …%o3 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o2, <4 x i32> %rsrc, i32 0, i32 %voffset, …
27 …%o4 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o3, <4 x i32> %rsrc, i32 %vindex, i32 %vof…
29 …%o5 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o4, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1…
30 …%o6 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o5, <4 x i32> %rsrc, i32 0, i32 8192, i1 0)
31 …%unused = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o6, <4 x i32> %rsrc, i32 0, i32 0, i1 …
36 ;CHECK-LABEL: {{^}}test11:
37 ;CHECK-NOT: s_waitcnt
38 ;CHECK: buffer_atomic_swap_x2 v[3:4], off, s[0:3], 0 glc
39 ;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
41 ;CHECK: buffer_atomic_swap_x2 v[3:4], v1, s[0:3], 0 idxen glc
43 ;CHECK: buffer_atomic_swap_x2 v[3:4], v2, s[0:3], 0 offen glc
45 ;CHECK: buffer_atomic_swap_x2 v[3:4], v[1:2], s[0:3], 0 idxen offen glc
47 ;CHECK: buffer_atomic_swap_x2 v[3:4], v2, s[0:3], 0 offen offset:42 glc
48 ;CHECK-DAG: s_waitcnt vmcnt(0)
49 ;SICI: buffer_atomic_swap_x2 v[3:4], v0, s[0:3], 0 offen glc
50 ;VI: buffer_atomic_swap_x2 v[3:4], off, s[0:3], [[SOFS]] offset:4 glc
52 ;CHECK: buffer_atomic_swap_x2 v[3:4], off, s[0:3], 0{{$}}
56   %o1 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o0, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
57 …%o2 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o1, <4 x i32> %rsrc, i32 %vindex, i32 0, i…
58 …%o3 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o2, <4 x i32> %rsrc, i32 0, i32 %voffset, …
59 …%o4 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o3, <4 x i32> %rsrc, i32 %vindex, i32 %vof…
61 …%o5 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o4, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1…
62 …%o6 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o5, <4 x i32> %rsrc, i32 0, i32 8192, i1 0)
63 …%unused = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o6, <4 x i32> %rsrc, i32 0, i32 0, i1 …
69 ;CHECK-LABEL: {{^}}test2:
70 ;CHECK-NOT: s_waitcnt
71 ;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc
73 ;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc
75 ;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 idxen glc
77 ;CHECK: buffer_atomic_umin v0, v1, s[0:3], 0 idxen glc
79 ;CHECK: buffer_atomic_smax v0, v1, s[0:3], 0 idxen glc
81 ;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 idxen glc
83 ;CHECK: buffer_atomic_and v0, v1, s[0:3], 0 idxen glc
85 ;CHECK: buffer_atomic_or v0, v1, s[0:3], 0 idxen glc
87 ;CHECK: buffer_atomic_xor v0, v1, s[0:3], 0 idxen glc
90 …%t1 = call i32 @llvm.amdgcn.buffer.atomic.add.i32(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 0, …
91 …%t2 = call i32 @llvm.amdgcn.buffer.atomic.sub.i32(i32 %t1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1…
92 …%t3 = call i32 @llvm.amdgcn.buffer.atomic.smin.i32(i32 %t2, <4 x i32> %rsrc, i32 %vindex, i32 0, i…
93 …%t4 = call i32 @llvm.amdgcn.buffer.atomic.umin.i32(i32 %t3, <4 x i32> %rsrc, i32 %vindex, i32 0, i…
94 …%t5 = call i32 @llvm.amdgcn.buffer.atomic.smax.i32(i32 %t4, <4 x i32> %rsrc, i32 %vindex, i32 0, i…
95 …%t6 = call i32 @llvm.amdgcn.buffer.atomic.umax.i32(i32 %t5, <4 x i32> %rsrc, i32 %vindex, i32 0, i…
96 …%t7 = call i32 @llvm.amdgcn.buffer.atomic.and.i32(i32 %t6, <4 x i32> %rsrc, i32 %vindex, i32 0, i1…
97 …%t8 = call i32 @llvm.amdgcn.buffer.atomic.or.i32(i32 %t7, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 …
98 …%t9 = call i32 @llvm.amdgcn.buffer.atomic.xor.i32(i32 %t8, <4 x i32> %rsrc, i32 %vindex, i32 0, i1…
103 ;CHECK-LABEL: {{^}}test3:
104 ;CHECK-NOT: s_waitcnt
105 ;CHECK: buffer_atomic_add_x2 v[0:1], v2, s[0:3], 0 idxen glc
107 ;CHECK: buffer_atomic_sub_x2 v[0:1], v2, s[0:3], 0 idxen glc
109 ;CHECK: buffer_atomic_smin_x2 v[0:1], v2, s[0:3], 0 idxen glc
111 ;CHECK: buffer_atomic_umin_x2 v[0:1], v2, s[0:3], 0 idxen glc
113 ;CHECK: buffer_atomic_smax_x2 v[0:1], v2, s[0:3], 0 idxen glc
115 ;CHECK: buffer_atomic_umax_x2 v[0:1], v2, s[0:3], 0 idxen glc
117 ;CHECK: buffer_atomic_and_x2 v[0:1], v2, s[0:3], 0 idxen glc
119 ;CHECK: buffer_atomic_or_x2 v[0:1], v2, s[0:3], 0 idxen glc
121 ;CHECK: buffer_atomic_xor_x2 v[0:1], v2, s[0:3], 0 idxen glc
125 …%t1 = call i64 @llvm.amdgcn.buffer.atomic.add.i64(i64 %t0, <4 x i32> %rsrc, i32 %vindex, i32 0, i1…
126 …%t2 = call i64 @llvm.amdgcn.buffer.atomic.sub.i64(i64 %t1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1…
127 …%t3 = call i64 @llvm.amdgcn.buffer.atomic.smin.i64(i64 %t2, <4 x i32> %rsrc, i32 %vindex, i32 0, i…
128 …%t4 = call i64 @llvm.amdgcn.buffer.atomic.umin.i64(i64 %t3, <4 x i32> %rsrc, i32 %vindex, i32 0, i…
129 …%t5 = call i64 @llvm.amdgcn.buffer.atomic.smax.i64(i64 %t4, <4 x i32> %rsrc, i32 %vindex, i32 0, i…
130 …%t6 = call i64 @llvm.amdgcn.buffer.atomic.umax.i64(i64 %t5, <4 x i32> %rsrc, i32 %vindex, i32 0, i…
131 …%t7 = call i64 @llvm.amdgcn.buffer.atomic.and.i64(i64 %t6, <4 x i32> %rsrc, i32 %vindex, i32 0, i1…
132 …%t8 = call i64 @llvm.amdgcn.buffer.atomic.or.i64(i64 %t7, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 …
133 …%t9 = call i64 @llvm.amdgcn.buffer.atomic.xor.i64(i64 %t8, <4 x i32> %rsrc, i32 %vindex, i32 0, i1…
143 ;CHECK-LABEL: {{^}}test4:
144 ;CHECK-NOT: s_waitcnt
145 ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 0 glc
147 ;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
148 ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v2, s[0:3], 0 idxen glc
150 ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen glc
152 ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v[2:3], s[0:3], 0 idxen offen glc
154 ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen offset:44 glc
155 ;CHECK-DAG: s_waitcnt vmcnt(0)
156 ;SICI: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 offen glc
157 ;VI: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[SOFS]] offset:4 glc
160 …%o1 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %data, i32 %cmp, <4 x i32> %rsrc, i32 0, i32…
161 …%o2 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o1, i32 %cmp, <4 x i32> %rsrc, i32 %vindex,…
162 …%o3 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o2, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %…
163 …%o4 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o3, i32 %cmp, <4 x i32> %rsrc, i32 %vindex,…
165 …%o5 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o4, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %…
166 …%o6 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o5, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 8…
168 ; Detecting the no-return variant doesn't work right now because of how the
170 ; Since there probably isn't a reasonable use-case of cmpswap that discards
173 ;  %unused = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o6, i32 %cmp, <4 x i32> %rsrc, i32 0,…
178 ;CHECK-LABEL: {{^}}test7:
182   %v = call i32 @llvm.amdgcn.buffer.atomic.add.i32(i32 1, <4 x i32> undef, i32 0, i32 4, i1 false)
187 declare i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32, <4 x i32>, i32, i32, i1) #0
188 declare i32 @llvm.amdgcn.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i1) #0
189 declare i32 @llvm.amdgcn.buffer.atomic.sub.i32(i32, <4 x i32>, i32, i32, i1) #0
190 declare i32 @llvm.amdgcn.buffer.atomic.smin.i32(i32, <4 x i32>, i32, i32, i1) #0
191 declare i32 @llvm.amdgcn.buffer.atomic.umin.i32(i32, <4 x i32>, i32, i32, i1) #0
192 declare i32 @llvm.amdgcn.buffer.atomic.smax.i32(i32, <4 x i32>, i32, i32, i1) #0
193 declare i32 @llvm.amdgcn.buffer.atomic.umax.i32(i32, <4 x i32>, i32, i32, i1) #0
194 declare i32 @llvm.amdgcn.buffer.atomic.and.i32(i32, <4 x i32>, i32, i32, i1) #0
195 declare i32 @llvm.amdgcn.buffer.atomic.or.i32(i32, <4 x i32>, i32, i32, i1) #0
196 declare i32 @llvm.amdgcn.buffer.atomic.xor.i32(i32, <4 x i32>, i32, i32, i1) #0
197 declare i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32, i32, <4 x i32>, i32, i32, i1) #0
198 declare i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64, <4 x i32>, i32, i32, i1) #0
199 declare i64 @llvm.amdgcn.buffer.atomic.add.i64(i64, <4 x i32>, i32, i32, i1) #0
200 declare i64 @llvm.amdgcn.buffer.atomic.sub.i64(i64, <4 x i32>, i32, i32, i1) #0
201 declare i64 @llvm.amdgcn.buffer.atomic.smin.i64(i64, <4 x i32>, i32, i32, i1) #0
202 declare i64 @llvm.amdgcn.buffer.atomic.umin.i64(i64, <4 x i32>, i32, i32, i1) #0
203 declare i64 @llvm.amdgcn.buffer.atomic.smax.i64(i64, <4 x i32>, i32, i32, i1) #0
204 declare i64 @llvm.amdgcn.buffer.atomic.umax.i64(i64, <4 x i32>, i32, i32, i1) #0
205 declare i64 @llvm.amdgcn.buffer.atomic.and.i64(i64, <4 x i32>, i32, i32, i1) #0
206 declare i64 @llvm.amdgcn.buffer.atomic.or.i64(i64, <4 x i32>, i32, i32, i1) #0
207 declare i64 @llvm.amdgcn.buffer.atomic.xor.i64(i64, <4 x i32>, i32, i32, i1) #0