Lines Matching full:float
80 define amdgpu_ps float @ps_main(i32 %idx) {
81 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
82 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
83 %r = fadd float %v1, %v2
84 ret float %r
131 define amdgpu_vs float @vs_main(i32 %idx) {
132 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
133 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
134 %r = fadd float %v1, %v2
135 ret float %r
177 define amdgpu_cs float @cs_main(i32 %idx) {
178 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
179 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
180 %r = fadd float %v1, %v2
181 ret float %r
206 define amdgpu_hs float @hs_main(i32 %idx) {
207 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
208 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
209 %r = fadd float %v1, %v2
210 ret float %r
254 define amdgpu_gs float @gs_main(i32 %idx) {
255 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
256 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
257 %r = fadd float %v1, %v2
258 ret float %r
311 define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg, i32 inreg, i32 inre…
312 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
313 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
314 %f = fadd float %v1, %v2
315 %r1 = insertvalue <{i32, i32, i32, float}> undef, i32 %swo, 2
316 %r2 = insertvalue <{i32, i32, i32, float}> %r1, float %f, 3
317 ret <{i32, i32, i32, float}> %r2
363 define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg, i32 inreg, i32 inre…
364 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
365 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
366 %f = fadd float %v1, %v2
367 %r1 = insertvalue <{i32, i32, i32, float}> undef, i32 %swo, 2
368 %r2 = insertvalue <{i32, i32, i32, float}> %r1, float %f, 3
369 ret <{i32, i32, i32, float}> %r2