Lines Matching refs:RV32

3 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32
26 ; CHECK-RV32-LABEL: foo_i32:
27 ; CHECK-RV32:       # %bb.0:
28 ; CHECK-RV32-NEXT:    addi sp, sp, -16
29 ; CHECK-RV32-NEXT:    sw a0, 12(sp)
30 ; CHECK-RV32-NEXT:    sw a1, 8(sp)
31 ; CHECK-RV32-NEXT:    lui a0, %hi(a)
32 ; CHECK-RV32-NEXT:    lw a0, %lo(a)(a0)
33 ; CHECK-RV32-NEXT:    lui a1, %hi(b)
34 ; CHECK-RV32-NEXT:    lw a1, %lo(b)(a1)
35 ; CHECK-RV32-NEXT:    add a0, a1, a0
36 ; CHECK-RV32-NEXT:    lui a1, %hi(c)
37 ; CHECK-RV32-NEXT:    sw a0, %lo(c)(a1)
38 ; CHECK-RV32-NEXT:    lw a1, 8(sp)
39 ; CHECK-RV32-NEXT:    lw a0, 12(sp)
40 ; CHECK-RV32-NEXT:    addi sp, sp, 16
41 ; CHECK-RV32-NEXT:    mret
88 ; CHECK-RV32-LABEL: foo_fp_i32:
89 ; CHECK-RV32:       # %bb.0:
90 ; CHECK-RV32-NEXT:    addi sp, sp, -16
91 ; CHECK-RV32-NEXT:    sw ra, 12(sp)
92 ; CHECK-RV32-NEXT:    sw s0, 8(sp)
93 ; CHECK-RV32-NEXT:    sw a0, 4(sp)
94 ; CHECK-RV32-NEXT:    sw a1, 0(sp)
95 ; CHECK-RV32-NEXT:    addi s0, sp, 16
96 ; CHECK-RV32-NEXT:    lui a0, %hi(a)
97 ; CHECK-RV32-NEXT:    lw a0, %lo(a)(a0)
98 ; CHECK-RV32-NEXT:    lui a1, %hi(b)
99 ; CHECK-RV32-NEXT:    lw a1, %lo(b)(a1)
100 ; CHECK-RV32-NEXT:    add a0, a1, a0
101 ; CHECK-RV32-NEXT:    lui a1, %hi(c)
102 ; CHECK-RV32-NEXT:    sw a0, %lo(c)(a1)
103 ; CHECK-RV32-NEXT:    lw a1, 0(sp)
104 ; CHECK-RV32-NEXT:    lw a0, 4(sp)
105 ; CHECK-RV32-NEXT:    lw s0, 8(sp)
106 ; CHECK-RV32-NEXT:    lw ra, 12(sp)
107 ; CHECK-RV32-NEXT:    addi sp, sp, 16
108 ; CHECK-RV32-NEXT:    mret
165 ; CHECK-RV32-LABEL: foo_float:
166 ; CHECK-RV32:       # %bb.0:
167 ; CHECK-RV32-NEXT:    addi sp, sp, -64
168 ; CHECK-RV32-NEXT:    sw ra, 60(sp)
169 ; CHECK-RV32-NEXT:    sw t0, 56(sp)
170 ; CHECK-RV32-NEXT:    sw t1, 52(sp)
171 ; CHECK-RV32-NEXT:    sw t2, 48(sp)
172 ; CHECK-RV32-NEXT:    sw a0, 44(sp)
173 ; CHECK-RV32-NEXT:    sw a1, 40(sp)
174 ; CHECK-RV32-NEXT:    sw a2, 36(sp)
175 ; CHECK-RV32-NEXT:    sw a3, 32(sp)
176 ; CHECK-RV32-NEXT:    sw a4, 28(sp)
177 ; CHECK-RV32-NEXT:    sw a5, 24(sp)
178 ; CHECK-RV32-NEXT:    sw a6, 20(sp)
179 ; CHECK-RV32-NEXT:    sw a7, 16(sp)
180 ; CHECK-RV32-NEXT:    sw t3, 12(sp)
181 ; CHECK-RV32-NEXT:    sw t4, 8(sp)
182 ; CHECK-RV32-NEXT:    sw t5, 4(sp)
183 ; CHECK-RV32-NEXT:    sw t6, 0(sp)
184 ; CHECK-RV32-NEXT:    lui a0, %hi(e)
185 ; CHECK-RV32-NEXT:    lw a0, %lo(e)(a0)
186 ; CHECK-RV32-NEXT:    lui a1, %hi(f)
187 ; CHECK-RV32-NEXT:    lw a1, %lo(f)(a1)
188 ; CHECK-RV32-NEXT:    call __addsf3
189 ; CHECK-RV32-NEXT:    lui a1, %hi(d)
190 ; CHECK-RV32-NEXT:    sw a0, %lo(d)(a1)
191 ; CHECK-RV32-NEXT:    lw t6, 0(sp)
192 ; CHECK-RV32-NEXT:    lw t5, 4(sp)
193 ; CHECK-RV32-NEXT:    lw t4, 8(sp)
194 ; CHECK-RV32-NEXT:    lw t3, 12(sp)
195 ; CHECK-RV32-NEXT:    lw a7, 16(sp)
196 ; CHECK-RV32-NEXT:    lw a6, 20(sp)
197 ; CHECK-RV32-NEXT:    lw a5, 24(sp)
198 ; CHECK-RV32-NEXT:    lw a4, 28(sp)
199 ; CHECK-RV32-NEXT:    lw a3, 32(sp)
200 ; CHECK-RV32-NEXT:    lw a2, 36(sp)
201 ; CHECK-RV32-NEXT:    lw a1, 40(sp)
202 ; CHECK-RV32-NEXT:    lw a0, 44(sp)
203 ; CHECK-RV32-NEXT:    lw t2, 48(sp)
204 ; CHECK-RV32-NEXT:    lw t1, 52(sp)
205 ; CHECK-RV32-NEXT:    lw t0, 56(sp)
206 ; CHECK-RV32-NEXT:    lw ra, 60(sp)
207 ; CHECK-RV32-NEXT:    addi sp, sp, 64
208 ; CHECK-RV32-NEXT:    mret
258 ; CHECK-RV32-LABEL: foo_fp_float:
259 ; CHECK-RV32:       # %bb.0:
260 ; CHECK-RV32-NEXT:    addi sp, sp, -80
261 ; CHECK-RV32-NEXT:    sw ra, 76(sp)
262 ; CHECK-RV32-NEXT:    sw t0, 72(sp)
263 ; CHECK-RV32-NEXT:    sw t1, 68(sp)
264 ; CHECK-RV32-NEXT:    sw t2, 64(sp)
265 ; CHECK-RV32-NEXT:    sw s0, 60(sp)
266 ; CHECK-RV32-NEXT:    sw a0, 56(sp)
267 ; CHECK-RV32-NEXT:    sw a1, 52(sp)
268 ; CHECK-RV32-NEXT:    sw a2, 48(sp)
269 ; CHECK-RV32-NEXT:    sw a3, 44(sp)
270 ; CHECK-RV32-NEXT:    sw a4, 40(sp)
271 ; CHECK-RV32-NEXT:    sw a5, 36(sp)
272 ; CHECK-RV32-NEXT:    sw a6, 32(sp)
273 ; CHECK-RV32-NEXT:    sw a7, 28(sp)
274 ; CHECK-RV32-NEXT:    sw t3, 24(sp)
275 ; CHECK-RV32-NEXT:    sw t4, 20(sp)
276 ; CHECK-RV32-NEXT:    sw t5, 16(sp)
277 ; CHECK-RV32-NEXT:    sw t6, 12(sp)
278 ; CHECK-RV32-NEXT:    addi s0, sp, 80
279 ; CHECK-RV32-NEXT:    lui a0, %hi(e)
280 ; CHECK-RV32-NEXT:    lw a0, %lo(e)(a0)
281 ; CHECK-RV32-NEXT:    lui a1, %hi(f)
282 ; CHECK-RV32-NEXT:    lw a1, %lo(f)(a1)
283 ; CHECK-RV32-NEXT:    call __addsf3
284 ; CHECK-RV32-NEXT:    lui a1, %hi(d)
285 ; CHECK-RV32-NEXT:    sw a0, %lo(d)(a1)
286 ; CHECK-RV32-NEXT:    lw t6, 12(sp)
287 ; CHECK-RV32-NEXT:    lw t5, 16(sp)
288 ; CHECK-RV32-NEXT:    lw t4, 20(sp)
289 ; CHECK-RV32-NEXT:    lw t3, 24(sp)
290 ; CHECK-RV32-NEXT:    lw a7, 28(sp)
291 ; CHECK-RV32-NEXT:    lw a6, 32(sp)
292 ; CHECK-RV32-NEXT:    lw a5, 36(sp)
293 ; CHECK-RV32-NEXT:    lw a4, 40(sp)
294 ; CHECK-RV32-NEXT:    lw a3, 44(sp)
295 ; CHECK-RV32-NEXT:    lw a2, 48(sp)
296 ; CHECK-RV32-NEXT:    lw a1, 52(sp)
297 ; CHECK-RV32-NEXT:    lw a0, 56(sp)
298 ; CHECK-RV32-NEXT:    lw s0, 60(sp)
299 ; CHECK-RV32-NEXT:    lw t2, 64(sp)
300 ; CHECK-RV32-NEXT:    lw t1, 68(sp)
301 ; CHECK-RV32-NEXT:    lw t0, 72(sp)
302 ; CHECK-RV32-NEXT:    lw ra, 76(sp)
303 ; CHECK-RV32-NEXT:    addi sp, sp, 80
304 ; CHECK-RV32-NEXT:    mret
365 ; CHECK-RV32-LABEL: foo_double:
366 ; CHECK-RV32:       # %bb.0:
367 ; CHECK-RV32-NEXT:    addi sp, sp, -64
368 ; CHECK-RV32-NEXT:    sw ra, 60(sp)
369 ; CHECK-RV32-NEXT:    sw t0, 56(sp)
370 ; CHECK-RV32-NEXT:    sw t1, 52(sp)
371 ; CHECK-RV32-NEXT:    sw t2, 48(sp)
372 ; CHECK-RV32-NEXT:    sw a0, 44(sp)
373 ; CHECK-RV32-NEXT:    sw a1, 40(sp)
374 ; CHECK-RV32-NEXT:    sw a2, 36(sp)
375 ; CHECK-RV32-NEXT:    sw a3, 32(sp)
376 ; CHECK-RV32-NEXT:    sw a4, 28(sp)
377 ; CHECK-RV32-NEXT:    sw a5, 24(sp)
378 ; CHECK-RV32-NEXT:    sw a6, 20(sp)
379 ; CHECK-RV32-NEXT:    sw a7, 16(sp)
380 ; CHECK-RV32-NEXT:    sw t3, 12(sp)
381 ; CHECK-RV32-NEXT:    sw t4, 8(sp)
382 ; CHECK-RV32-NEXT:    sw t5, 4(sp)
383 ; CHECK-RV32-NEXT:    sw t6, 0(sp)
384 ; CHECK-RV32-NEXT:    lui a1, %hi(h)
385 ; CHECK-RV32-NEXT:    lw a0, %lo(h)(a1)
386 ; CHECK-RV32-NEXT:    lw a1, %lo(h+4)(a1)
387 ; CHECK-RV32-NEXT:    lui a3, %hi(i)
388 ; CHECK-RV32-NEXT:    lw a2, %lo(i)(a3)
389 ; CHECK-RV32-NEXT:    lw a3, %lo(i+4)(a3)
390 ; CHECK-RV32-NEXT:    call __adddf3
391 ; CHECK-RV32-NEXT:    lui a2, %hi(g)
392 ; CHECK-RV32-NEXT:    sw a1, %lo(g+4)(a2)
393 ; CHECK-RV32-NEXT:    sw a0, %lo(g)(a2)
394 ; CHECK-RV32-NEXT:    lw t6, 0(sp)
395 ; CHECK-RV32-NEXT:    lw t5, 4(sp)
396 ; CHECK-RV32-NEXT:    lw t4, 8(sp)
397 ; CHECK-RV32-NEXT:    lw t3, 12(sp)
398 ; CHECK-RV32-NEXT:    lw a7, 16(sp)
399 ; CHECK-RV32-NEXT:    lw a6, 20(sp)
400 ; CHECK-RV32-NEXT:    lw a5, 24(sp)
401 ; CHECK-RV32-NEXT:    lw a4, 28(sp)
402 ; CHECK-RV32-NEXT:    lw a3, 32(sp)
403 ; CHECK-RV32-NEXT:    lw a2, 36(sp)
404 ; CHECK-RV32-NEXT:    lw a1, 40(sp)
405 ; CHECK-RV32-NEXT:    lw a0, 44(sp)
406 ; CHECK-RV32-NEXT:    lw t2, 48(sp)
407 ; CHECK-RV32-NEXT:    lw t1, 52(sp)
408 ; CHECK-RV32-NEXT:    lw t0, 56(sp)
409 ; CHECK-RV32-NEXT:    lw ra, 60(sp)
410 ; CHECK-RV32-NEXT:    addi sp, sp, 64
411 ; CHECK-RV32-NEXT:    mret
554 ; CHECK-RV32-LABEL: foo_fp_double:
555 ; CHECK-RV32:       # %bb.0:
556 ; CHECK-RV32-NEXT:    addi sp, sp, -80
557 ; CHECK-RV32-NEXT:    sw ra, 76(sp)
558 ; CHECK-RV32-NEXT:    sw t0, 72(sp)
559 ; CHECK-RV32-NEXT:    sw t1, 68(sp)
560 ; CHECK-RV32-NEXT:    sw t2, 64(sp)
561 ; CHECK-RV32-NEXT:    sw s0, 60(sp)
562 ; CHECK-RV32-NEXT:    sw a0, 56(sp)
563 ; CHECK-RV32-NEXT:    sw a1, 52(sp)
564 ; CHECK-RV32-NEXT:    sw a2, 48(sp)
565 ; CHECK-RV32-NEXT:    sw a3, 44(sp)
566 ; CHECK-RV32-NEXT:    sw a4, 40(sp)
567 ; CHECK-RV32-NEXT:    sw a5, 36(sp)
568 ; CHECK-RV32-NEXT:    sw a6, 32(sp)
569 ; CHECK-RV32-NEXT:    sw a7, 28(sp)
570 ; CHECK-RV32-NEXT:    sw t3, 24(sp)
571 ; CHECK-RV32-NEXT:    sw t4, 20(sp)
572 ; CHECK-RV32-NEXT:    sw t5, 16(sp)
573 ; CHECK-RV32-NEXT:    sw t6, 12(sp)
574 ; CHECK-RV32-NEXT:    addi s0, sp, 80
575 ; CHECK-RV32-NEXT:    lui a1, %hi(h)
576 ; CHECK-RV32-NEXT:    lw a0, %lo(h)(a1)
577 ; CHECK-RV32-NEXT:    lw a1, %lo(h+4)(a1)
578 ; CHECK-RV32-NEXT:    lui a3, %hi(i)
579 ; CHECK-RV32-NEXT:    lw a2, %lo(i)(a3)
580 ; CHECK-RV32-NEXT:    lw a3, %lo(i+4)(a3)
581 ; CHECK-RV32-NEXT:    call __adddf3
582 ; CHECK-RV32-NEXT:    lui a2, %hi(g)
583 ; CHECK-RV32-NEXT:    sw a1, %lo(g+4)(a2)
584 ; CHECK-RV32-NEXT:    sw a0, %lo(g)(a2)
585 ; CHECK-RV32-NEXT:    lw t6, 12(sp)
586 ; CHECK-RV32-NEXT:    lw t5, 16(sp)
587 ; CHECK-RV32-NEXT:    lw t4, 20(sp)
588 ; CHECK-RV32-NEXT:    lw t3, 24(sp)
589 ; CHECK-RV32-NEXT:    lw a7, 28(sp)
590 ; CHECK-RV32-NEXT:    lw a6, 32(sp)
591 ; CHECK-RV32-NEXT:    lw a5, 36(sp)
592 ; CHECK-RV32-NEXT:    lw a4, 40(sp)
593 ; CHECK-RV32-NEXT:    lw a3, 44(sp)
594 ; CHECK-RV32-NEXT:    lw a2, 48(sp)
595 ; CHECK-RV32-NEXT:    lw a1, 52(sp)
596 ; CHECK-RV32-NEXT:    lw a0, 56(sp)
597 ; CHECK-RV32-NEXT:    lw s0, 60(sp)
598 ; CHECK-RV32-NEXT:    lw t2, 64(sp)
599 ; CHECK-RV32-NEXT:    lw t1, 68(sp)
600 ; CHECK-RV32-NEXT:    lw t0, 72(sp)
601 ; CHECK-RV32-NEXT:    lw ra, 76(sp)
602 ; CHECK-RV32-NEXT:    addi sp, sp, 80
603 ; CHECK-RV32-NEXT:    mret