Lines Matching refs:TMP2

7 ; CHECK-NEXT:    [[TMP2:%.*]] = shl i8 [[Y:%.*]], 2
8 ; CHECK-NEXT:    [[SH1:%.*]] = and i8 [[TMP1]], [[TMP2]]
20 ; CHECK-NEXT:    [[TMP2:%.*]] = shl <2 x i8> [[Y:%.*]], <i8 2, i8 0>
21 ; CHECK-NEXT:    [[SH1:%.*]] = and <2 x i8> [[TMP1]], [[TMP2]]
34 ; CHECK-NEXT:    [[TMP2:%.*]] = shl nsw i16 [[Y]], 7
35 ; CHECK-NEXT:    [[SH1:%.*]] = or i16 [[TMP1]], [[TMP2]]
49 ; CHECK-NEXT:    [[TMP2:%.*]] = shl <2 x i16> [[Y]], <i16 7, i16 undef>
50 ; CHECK-NEXT:    [[SH1:%.*]] = or <2 x i16> [[TMP1]], [[TMP2]]
63 ; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[Y:%.*]], 7
64 ; CHECK-NEXT:    [[SH1:%.*]] = xor i32 [[TMP1]], [[TMP2]]
76 ; CHECK-NEXT:    [[TMP2:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 7, i32 8>
77 ; CHECK-NEXT:    [[SH1:%.*]] = xor <2 x i32> [[TMP1]], [[TMP2]]
90 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i64 [[Y]], 7
91 ; CHECK-NEXT:    [[SH1:%.*]] = and i64 [[TMP1]], [[TMP2]]
105 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr <2 x i64> [[Y]], <i64 7, i64 undef>
106 ; CHECK-NEXT:    [[SH1:%.*]] = and <2 x i64> [[TMP1]], [[TMP2]]
119 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr <4 x i32> [[Y:%.*]], <i32 7, i32 7, i32 7, i32 7>
120 ; CHECK-NEXT:    [[SH1:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]
133 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr <8 x i16> [[Y]], <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i1…
134 ; CHECK-NEXT:    [[SH1:%.*]] = xor <8 x i16> [[TMP1]], [[TMP2]]
148 ; CHECK-NEXT:    [[TMP2:%.*]] = ashr <16 x i8> [[Y]], <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8…
149 ; CHECK-NEXT:    [[SH1:%.*]] = and <16 x i8> [[TMP1]], [[TMP2]]
162 ; CHECK-NEXT:    [[TMP2:%.*]] = ashr <2 x i64> [[Y:%.*]], <i64 7, i64 7>
163 ; CHECK-NEXT:    [[SH1:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]]
176 ; CHECK-NEXT:    [[TMP2:%.*]] = ashr i32 [[Y]], 7
177 ; CHECK-NEXT:    [[SH1:%.*]] = xor i32 [[TMP1]], [[TMP2]]