Lines Matching refs:ult
11 ; %r = icmp ult i32 %t, 256
33 ; %r = icmp ult i32 %arg, 128
41 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
46 %t3 = icmp ult i32 %t2, 256
53 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
59 %t4 = icmp ult i32 %t3, 256
66 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
69 %t1 = icmp ult i32 %arg, 512
71 %t3 = icmp ult i32 %t2, 256
79 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
82 %t1 = icmp ult i32 %arg, 128
84 %t3 = icmp ult i32 %t2, 512
95 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
101 %t3 = icmp ult i32 %t2, 256
113 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <2 x i32> [[ARG:%.*]], <i32 128, i32 128>
118 %t3 = icmp ult <2 x i32> %t2, <i32 256, i32 256>
127 ; CHECK-NEXT: [[T3:%.*]] = icmp ult <2 x i32> [[T2]], <i32 256, i32 512>
133 %t3 = icmp ult <2 x i32> %t2, <i32 256, i32 512>
142 ; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 256, i32 256>
148 %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 256, i32 256>
157 ; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 256, i32 256>
163 %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 256, i32 256>
172 ; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 undef, i32 256>
178 %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 undef, i32 256>
187 ; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 256, i32 256>
193 %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 256, i32 256>
202 ; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 undef, i32 256>
208 %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 undef, i32 256>
217 ; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 undef, i32 256>
223 %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 undef, i32 256>
232 ; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 undef, i32 256>
238 %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 undef, i32 256>
252 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
258 %t3 = icmp ult i32 %t2, 256
266 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
270 %t1 = icmp ult i32 %arg, 512
272 %t3 = icmp ult i32 %t2, 256
283 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
289 %t4 = icmp ult i32 %t3, 256
297 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i16 [[T1]], 128
303 %t4 = icmp ult i16 %t3, 256
314 ; CHECK-NEXT: [[T5:%.*]] = icmp ult i16 [[T4]], 256
322 %t5 = icmp ult i16 %t4, 256
345 ; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
347 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
354 %t3 = icmp ult i32 %t2, 256
368 ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
370 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
379 %t4 = icmp ult i32 %t3, 256
451 ; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
457 %t3 = icmp ult i32 %t2, 256
467 ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
474 %t4 = icmp ult i32 %t3, 256
484 ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
491 %t4 = icmp ult i32 %t3, 256
501 ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
508 %t4 = icmp ult i32 %t3, 256
518 ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
525 %t4 = icmp ult i32 %t3, 256
535 ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
542 %t4 = icmp ult i32 %t3, 256
553 %t3 = icmp ult i32 %t2, 256
562 ; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
568 %t3 = icmp ult i32 %t2, 256
577 ; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
583 %t3 = icmp ult i32 %t2, 256
592 ; CHECK-NEXT: [[T2:%.*]] = icmp ult i32 [[T1]], 1024
594 ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
599 %t2 = icmp ult i32 %t1, 1024
601 %t4 = icmp ult i32 %t3, 256
611 ; CHECK-NEXT: [[T4:%.*]] = icmp ult i16 [[T3]], 256
618 %t4 = icmp ult i16 %t3, 256